xref: /openbmc/u-boot/board/freescale/mx35pdk/mx35pdk.h (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2eae4988bSStefano Babic /*
3eae4988bSStefano Babic  *
4eae4988bSStefano Babic  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5eae4988bSStefano Babic  *
6eae4988bSStefano Babic  * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
7eae4988bSStefano Babic  */
8eae4988bSStefano Babic 
9eae4988bSStefano Babic #ifndef __BOARD_MX35_3STACK_H
10eae4988bSStefano Babic #define __BOARD_MX35_3STACK_H
11eae4988bSStefano Babic 
12eae4988bSStefano Babic #define DBG_BASE_ADDR		WEIM_CTRL_CS5
13eae4988bSStefano Babic #define DBG_CSCR_U_CONFIG	0x0000D843
14eae4988bSStefano Babic #define DBG_CSCR_L_CONFIG	0x22252521
15eae4988bSStefano Babic #define DBG_CSCR_A_CONFIG	0x22220A00
16eae4988bSStefano Babic 
17eae4988bSStefano Babic #define CCM_CCMR_CONFIG		0x003F4208
18eae4988bSStefano Babic #define CCM_PDR0_CONFIG		0x00801000
19eae4988bSStefano Babic 
20eae4988bSStefano Babic /* MEMORY SETTING */
21eae4988bSStefano Babic #define ESDCTL_0x92220000	0x92220000
22eae4988bSStefano Babic #define ESDCTL_0xA2220000	0xA2220000
23eae4988bSStefano Babic #define ESDCTL_0xB2220000	0xB2220000
24eae4988bSStefano Babic #define ESDCTL_0x82228080	0x82228080
25eae4988bSStefano Babic 
26eae4988bSStefano Babic #define ESDCTL_PRECHARGE	0x00000400
27eae4988bSStefano Babic 
28eae4988bSStefano Babic #define ESDCTL_MDDR_CONFIG	0x007FFC3F
29eae4988bSStefano Babic #define ESDCTL_MDDR_MR		0x00000033
30eae4988bSStefano Babic #define ESDCTL_MDDR_EMR		0x02000000
31eae4988bSStefano Babic 
32eae4988bSStefano Babic #define ESDCTL_DDR2_CONFIG	0x007FFC3F
33eae4988bSStefano Babic #define ESDCTL_DDR2_EMR2	0x04000000
34eae4988bSStefano Babic #define ESDCTL_DDR2_EMR3	0x06000000
35eae4988bSStefano Babic #define ESDCTL_DDR2_EN_DLL	0x02000400
36eae4988bSStefano Babic #define ESDCTL_DDR2_RESET_DLL	0x00000333
37eae4988bSStefano Babic #define ESDCTL_DDR2_MR		0x00000233
38eae4988bSStefano Babic #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
39eae4988bSStefano Babic 
40eae4988bSStefano Babic #define ESDCTL_DELAY_LINE5	0x00F49F00
41eae4988bSStefano Babic #endif				/* __BOARD_MX35_3STACK_H */
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