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Searched refs:DISPLAY_INFO (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_device.h36 #define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
37 #define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
40 #define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
44 #define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst)
47 #define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
51 #define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
55 #define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
57 #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
62 #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay)
63 #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr)
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H A Dintel_display_reg_defs.h11 #define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset)
39 #define _MMIO_PIPE2(pipe, reg) _MMIO(DISPLAY_INFO(dev_priv)->pipe_offsets[(pipe)] - \
40 DISPLAY_INFO(dev_priv)->pipe_offsets[PIPE_A] + \
42 #define _MMIO_TRANS2(tran, reg) _MMIO(DISPLAY_INFO(dev_priv)->trans_offsets[(tran)] - \
43 DISPLAY_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + \
45 #define _MMIO_CURSOR2(pipe, reg) _MMIO(DISPLAY_INFO(dev_priv)->cursor_offsets[(pipe)] - \
46 DISPLAY_INFO(dev_priv)->cursor_offsets[PIPE_A] + \
H A Dintel_hti.c18 if (DISPLAY_INFO(i915)->has_hti) in intel_hti_init()
H A Dintel_color.c1982 return DISPLAY_INFO(i915)->color.gamma_lut_tests; in intel_gamma_lut_tests()
1989 return DISPLAY_INFO(i915)->color.degamma_lut_tests; in intel_degamma_lut_tests()
2000 return DISPLAY_INFO(i915)->color.gamma_lut_size; in intel_gamma_lut_size()
2007 return DISPLAY_INFO(i915)->color.degamma_lut_size; in intel_degamma_lut_size()
2525 DISPLAY_INFO(i915)->color.degamma_lut_size, in glk_assign_luts()
3059 u32 lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size; in i9xx_read_lut_10()
3108 int i, lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size; in i965_read_lut_10p6()
3158 int i, lut_size = DISPLAY_INFO(dev_priv)->color.degamma_lut_size; in chv_read_cgm_degamma()
3184 int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size; in chv_read_cgm_gamma()
3248 int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size; in ilk_read_lut_10()
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H A Dintel_fb_pin.c246 DISPLAY_INFO(dev_priv)->cursor_needs_physical; in intel_plane_pin_fb()
H A Dintel_display_power.c1081 u8 slice_mask = DISPLAY_INFO(dev_priv)->dbuf.slice_mask; in gen9_dbuf_slices_update()
1150 unsigned long abox_regs = DISPLAY_INFO(dev_priv)->abox_mask; in icl_mbus_init()
1604 unsigned long abox_mask = DISPLAY_INFO(dev_priv)->abox_mask; in tgl_bw_buddy_init()
H A Dintel_display.h116 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
H A Dintel_cursor.c39 if (DISPLAY_INFO(dev_priv)->cursor_needs_physical) in intel_cursor_base()
H A Dskl_watermark.c510 return DISPLAY_INFO(i915)->dbuf.size / in intel_dbuf_slice_size()
511 hweight8(DISPLAY_INFO(i915)->dbuf.slice_mask); in intel_dbuf_slice_size()
530 WARN_ON(ddb->end > DISPLAY_INFO(i915)->dbuf.size); in skl_ddb_entry_for_slices()
2628 DISPLAY_INFO(i915)->dbuf.slice_mask, in skl_compute_ddb()
/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_device_info.c440 &DISPLAY_INFO(i915)->__runtime_defaults, in intel_device_info_driver_create()
H A Di915_debugfs.c70 intel_display_device_info_print(DISPLAY_INFO(i915), DISPLAY_RUNTIME_INFO(i915), &p); in i915_capabilities()
H A Di915_drv.h419 #define DISPLAY_INFO(i915) ((i915)->display.info.__device_info) macro
H A Di915_driver.c699 intel_display_device_info_print(DISPLAY_INFO(dev_priv), in i915_welcome_messages()
H A Di915_gpu_error.c2000 memcpy(&error->display_device_info, DISPLAY_INFO(i915), in capture_gen()