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Searched refs:DDR2 (Results 1 – 25 of 65) sorted by relevance

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/openbmc/u-boot/cmd/
H A Di2c.c1151 enum { unknown, EDO, SDRAM, DDR, DDR2, DDR3, DDR4 } type; in do_sdram() enumerator
1253 type = DDR2; in do_sdram()
1283 case DDR2: in do_sdram()
1293 case DDR2: in do_sdram()
1314 case DDR2: in do_sdram()
1325 case DDR2: in do_sdram()
1359 case DDR2: in do_sdram()
1372 case DDR2: in do_sdram()
1389 if (DDR2 != type) { in do_sdram()
1404 case DDR2: in do_sdram()
[all …]
/openbmc/qemu/hw/i2c/
H A Dsmbus_eeprom.c213 case DDR2: in spd_data_generate()
242 case DDR2: in spd_data_generate()
260 spd[5] = (type == DDR2 ? nbanks - 1 : nbanks); in spd_data_generate()
270 spd[15] = (type == DDR2 ? 0 : 1); /* reserved / delay for random col rd */ in spd_data_generate()
274 spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */ in spd_data_generate()
276 spd[21] = (type < DDR2 ? 0x20 : 0); /* module features */ in spd_data_generate()
/openbmc/u-boot/drivers/ddr/fsl/
H A DKconfig81 Enable Freescale DDR2 controller.
87 Enable Freescale DDR2 controller for MPC86xx SoCs.
137 bool "Freescale DDR2 controller"
/openbmc/u-boot/arch/mips/mach-mt7620/
H A DKconfig68 prompt "DDR2 size"
97 prompt "DDR2 chip width"
114 prompt "DDR2 bus width"
/openbmc/u-boot/board/Synology/ds109/
H A Dopenocd.cfg63 mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
64 mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
65 mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register
H A Dkwbimage.cfg27 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
120 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
121 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dprocessor.hpp46 DDR2, enumerator
132 {ProcessorMemoryType::DDR2, "DDR2"},
H A Dmemory.hpp23 DDR2, enumerator
126 {MemoryDeviceType::DDR2, "DDR2"},
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dbrcm,bcm2835-cprman.txt26 - DSI0 DDR2 clock
29 - DSI1 DDR2 clock
/openbmc/u-boot/board/woodburn/
H A Dimximage.cfg3 /* DDR2 init */
/openbmc/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg26 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
119 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
120 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg29 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
122 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
123 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
/openbmc/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg24 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
117 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
118 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
/openbmc/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg23 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
/openbmc/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg23 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
/openbmc/qemu/include/hw/i2c/
H A Dsmbus_eeprom.h33 enum sdram_type { SDR = 0x4, DDR = 0x7, DDR2 = 0x8 }; enumerator
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
H A Dkwbimage-is2.cfg24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
H A Dkwbimage-ns2l.cfg24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg27 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
120 DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
121 DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
/openbmc/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg23 # bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
116 DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
/openbmc/u-boot/board/Marvell/openrd/
H A Dkwbimage.cfg23 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
116 DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
/openbmc/u-boot/board/Barix/ipam390/
H A Dipam390-ais-uart.cfg58 ; for starting the DDR2 interface.
166 ; for starting the DDR2 interface on ARM-boot D800K002 devices.
183 ; for starting the DDR2 interface on DSP-boot D800K002 devices.
/openbmc/u-boot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg24 # bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
117 DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
118 DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)

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