103efcb05SHeiko Schocher; General settings that can be overwritten in the host code 203efcb05SHeiko Schocher; that calls the AISGen library. 303efcb05SHeiko Schocher[General] 403efcb05SHeiko Schocher 503efcb05SHeiko Schocher; Can be 8 or 16 - used in emifa 603efcb05SHeiko SchocherbusWidth=8 703efcb05SHeiko Schocher 803efcb05SHeiko Schocher; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW 903efcb05SHeiko SchocherBootMode=UART 1003efcb05SHeiko Schocher 1103efcb05SHeiko Schocher; 8,16,24 - used for SPI,I2C 1203efcb05SHeiko Schocher;AddrWidth=8 1303efcb05SHeiko Schocher 1403efcb05SHeiko Schocher; NO_CRC,SECTION_CRC,SINGLE_CRC 1503efcb05SHeiko SchochercrcCheckType=NO_CRC 1603efcb05SHeiko Schocher 1703efcb05SHeiko Schocher; This section allows setting the PLL0 system clock with a 1803efcb05SHeiko Schocher; specified multiplier and divider as shown. The clock source 1903efcb05SHeiko Schocher; can also be chosen for internal or external. 2003efcb05SHeiko Schocher; |------24|------16|-------8|-------0| 2103efcb05SHeiko Schocher; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV| 2203efcb05SHeiko Schocher; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7| 2303efcb05SHeiko Schocher;[PLL0CONFIG] 2403efcb05SHeiko Schocher;PLL0CFG0 = 0x00180001 2503efcb05SHeiko Schocher;PLL0CFG1 = 0x00000205 2603efcb05SHeiko Schocher 2703efcb05SHeiko Schocher[PLLANDCLOCKCONFIG] 2803efcb05SHeiko SchocherPLL0CFG0 = 0x00180001 2903efcb05SHeiko SchocherPLL0CFG1 = 0x00000205 3003efcb05SHeiko SchocherPERIPHCLKCFG = 0x00000051 3103efcb05SHeiko Schocher 3203efcb05SHeiko Schocher; This section allows setting up the PLL1. Usually this will 3303efcb05SHeiko Schocher; take place as part of the EMIF3a DDR setup. The format of 3403efcb05SHeiko Schocher; the input args is as follows: 3503efcb05SHeiko Schocher; |------24|------16|-------8|-------0| 3603efcb05SHeiko Schocher; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| 3703efcb05SHeiko Schocher; PLL1CFG1: | RSVD | PLLDIV3| 3803efcb05SHeiko Schocher[PLL1CONFIG] 3903efcb05SHeiko SchocherPLL1CFG0 = 0x18010001 4003efcb05SHeiko SchocherPLL1CFG1 = 0x00000002 4103efcb05SHeiko Schocher 4203efcb05SHeiko Schocher; This section lets us configure the peripheral interface 4303efcb05SHeiko Schocher; of the current booting peripheral (I2C, SPI, or UART). 4403efcb05SHeiko Schocher; Use with caution. The format of the PERIPHCLKCFG field 4503efcb05SHeiko Schocher; is as follows: 4603efcb05SHeiko Schocher; SPI: |------24|------16|-------8|-------0| 4703efcb05SHeiko Schocher; | RSVD |PRESCALE| 4803efcb05SHeiko Schocher; 4903efcb05SHeiko Schocher; I2C: |------24|------16|-------8|-------0| 5003efcb05SHeiko Schocher; | RSVD |PRESCALE| CLKL | CLKH | 5103efcb05SHeiko Schocher; 5203efcb05SHeiko Schocher; UART: |------24|------16|-------8|-------0| 5303efcb05SHeiko Schocher; | RSVD | OSR | DLH | DLL | 5403efcb05SHeiko Schocher[PERIPHCLKCFG] 5503efcb05SHeiko SchocherPERIPHCLKCFG = 0x00000051 5603efcb05SHeiko Schocher 5703efcb05SHeiko Schocher; This section can be used to configure the PLL1 and the EMIF3a registers 5803efcb05SHeiko Schocher; for starting the DDR2 interface. 5903efcb05SHeiko Schocher; See PLL1CONFIG section for the format of the PLL1CFG fields. 6003efcb05SHeiko Schocher; |------24|------16|-------8|-------0| 6103efcb05SHeiko Schocher; PLL1CFG0: | PLL1CFG | 6203efcb05SHeiko Schocher; PLL1CFG1: | PLL1CFG | 6303efcb05SHeiko Schocher; DDRPHYC1R: | DDRPHYC1R | 6403efcb05SHeiko Schocher; SDCR: | SDCR | 6503efcb05SHeiko Schocher; SDTIMR: | SDTIMR | 6603efcb05SHeiko Schocher; SDTIMR2: | SDTIMR2 | 6703efcb05SHeiko Schocher; SDRCR: | SDRCR | 6803efcb05SHeiko Schocher; CLK2XSRC: | CLK2XSRC | 6903efcb05SHeiko Schocher[EMIF3DDR] 7003efcb05SHeiko SchocherPLL1CFG0 = 0x18010001 7103efcb05SHeiko SchocherPLL1CFG1 = 0x00000002 7203efcb05SHeiko SchocherDDRPHYC1R = 0x000000C2 7303efcb05SHeiko SchocherSDCR = 0x0017C432 7403efcb05SHeiko SchocherSDTIMR = 0x26922A09 7503efcb05SHeiko SchocherSDTIMR2 = 0x4414C722 7603efcb05SHeiko SchocherSDRCR = 0x00000498 7703efcb05SHeiko SchocherCLK2XSRC = 0x00000000 7803efcb05SHeiko Schocher 7903efcb05SHeiko Schocher; This section can be used to configure the EMIFA to use 8003efcb05SHeiko Schocher; CS0 as an SDRAM interface. The fields required to do this 8103efcb05SHeiko Schocher; are given below. 8203efcb05SHeiko Schocher; |------24|------16|-------8|-------0| 8303efcb05SHeiko Schocher; SDBCR: | SDBCR | 8403efcb05SHeiko Schocher; SDTIMR: | SDTIMR | 8503efcb05SHeiko Schocher; SDRSRPDEXIT: | SDRSRPDEXIT | 8603efcb05SHeiko Schocher; SDRCR: | SDRCR | 8703efcb05SHeiko Schocher; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE | 8803efcb05SHeiko Schocher;[EMIF25SDRAM] 8903efcb05SHeiko Schocher;SDBCR = 0x00004421 9003efcb05SHeiko Schocher;SDTIMR = 0x42215810 9103efcb05SHeiko Schocher;SDRSRPDEXIT = 0x00000009 9203efcb05SHeiko Schocher;SDRCR = 0x00000410 9303efcb05SHeiko Schocher;DIV4p5_CLK_ENABLE = 0x00000001 9403efcb05SHeiko Schocher 9503efcb05SHeiko Schocher; This section can be used to configure the async chip selects 9603efcb05SHeiko Schocher; of the EMIFA (CS2-CS5). The fields required to do this 9703efcb05SHeiko Schocher; are given below. 9803efcb05SHeiko Schocher; |------24|------16|-------8|-------0| 9903efcb05SHeiko Schocher; A1CR: | A1CR | 10003efcb05SHeiko Schocher; A2CR: | A2CR | 10103efcb05SHeiko Schocher; A3CR: | A3CR | 10203efcb05SHeiko Schocher; A4CR: | A4CR | 10303efcb05SHeiko Schocher; NANDFCR: | NANDFCR | 10403efcb05SHeiko Schocher;[EMIF25ASYNC] 10503efcb05SHeiko Schocher;A1CR = 0x00000000 10603efcb05SHeiko Schocher;A2CR = 0x00000000 10703efcb05SHeiko Schocher;A3CR = 0x00000000 10803efcb05SHeiko Schocher;A4CR = 0x00000000 10903efcb05SHeiko Schocher;NANDFCR = 0x00000000 11003efcb05SHeiko Schocher[EMIF25ASYNC] 11103efcb05SHeiko SchocherA1CR = 0x00000000 112*660a2e65SHeiko SchocherA2CR = 0x04202110 11303efcb05SHeiko SchocherA3CR = 0x00000000 11403efcb05SHeiko SchocherA4CR = 0x00000000 11503efcb05SHeiko SchocherNANDFCR = 0x00000012 11603efcb05SHeiko Schocher 11703efcb05SHeiko Schocher; This section should be used in place of PLL0CONFIG when 11803efcb05SHeiko Schocher; the I2C, SPI, or UART modes are being used. This ensures that 11903efcb05SHeiko Schocher; the system PLL and the peripheral's clocks are changed together. 12003efcb05SHeiko Schocher; See PLL0CONFIG section for the format of the PLL0CFG fields. 12103efcb05SHeiko Schocher; See PERIPHCLKCFG section for the format of the CLKCFG field. 12203efcb05SHeiko Schocher; |------24|------16|-------8|-------0| 12303efcb05SHeiko Schocher; PLL0CFG0: | PLL0CFG | 12403efcb05SHeiko Schocher; PLL0CFG1: | PLL0CFG | 12503efcb05SHeiko Schocher; PERIPHCLKCFG: | CLKCFG | 12603efcb05SHeiko Schocher;[PLLANDCLOCKCONFIG] 12703efcb05SHeiko Schocher;PLL0CFG0 = 0x00180001 12803efcb05SHeiko Schocher;PLL0CFG1 = 0x00000205 12903efcb05SHeiko Schocher;PERIPHCLKCFG = 0x00010032 13003efcb05SHeiko Schocher 13103efcb05SHeiko Schocher; This section should be used to setup the power state of modules 13203efcb05SHeiko Schocher; of the two PSCs. This section can be included multiple times to 13303efcb05SHeiko Schocher; allow the configuration of any or all of the device modules. 13403efcb05SHeiko Schocher; |------24|------16|-------8|-------0| 13503efcb05SHeiko Schocher; LPSCCFG: | PSCNUM | MODULE | PD | STATE | 13603efcb05SHeiko Schocher;[PSCCONFIG] 13703efcb05SHeiko Schocher;LPSCCFG= 13803efcb05SHeiko Schocher 13903efcb05SHeiko Schocher; This section allows setting of a single PINMUX register. 14003efcb05SHeiko Schocher; This section can be included multiple times to allow setting 14103efcb05SHeiko Schocher; as many PINMUX registers as needed. 14203efcb05SHeiko Schocher; |------24|------16|-------8|-------0| 14303efcb05SHeiko Schocher; REGNUM: | regNum | 14403efcb05SHeiko Schocher; MASK: | mask | 14503efcb05SHeiko Schocher; VALUE: | value | 14603efcb05SHeiko Schocher;[PINMUX] 14703efcb05SHeiko Schocher;REGNUM = 5 14803efcb05SHeiko Schocher;MASK = 0x00FF0000 14903efcb05SHeiko Schocher;VALUE = 0x00880000 15003efcb05SHeiko Schocher 15103efcb05SHeiko Schocher; No Params required - simply include this section for the fast boot 15203efcb05SHeiko Schocher; function to be called 15303efcb05SHeiko Schocher;[FASTBOOT] 15403efcb05SHeiko Schocher 15503efcb05SHeiko Schocher; This section allows setting up the PLL1. Usually this will 15603efcb05SHeiko Schocher; take place as part of the EMIF3a DDR setup. The format of 15703efcb05SHeiko Schocher; the input args is as follows: 15803efcb05SHeiko Schocher; |------24|------16|-------8|-------0| 15903efcb05SHeiko Schocher; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| 16003efcb05SHeiko Schocher; PLL1CFG1: | RSVD | PLLDIV3| 16103efcb05SHeiko Schocher;[PLL1CONFIG] 16203efcb05SHeiko Schocher;PLL1CFG0 = 0x15010001 16303efcb05SHeiko Schocher;PLL1CFG1 = 0x00000002 16403efcb05SHeiko Schocher 16503efcb05SHeiko Schocher; This section can be used to configure the PLL1 and the EMIF3a registers 16603efcb05SHeiko Schocher; for starting the DDR2 interface on ARM-boot D800K002 devices. 16703efcb05SHeiko Schocher; |------24|------16|-------8|-------0| 16803efcb05SHeiko Schocher; DDRPHYC1R: | DDRPHYC1R | 16903efcb05SHeiko Schocher; SDCR: | SDCR | 17003efcb05SHeiko Schocher; SDTIMR: | SDTIMR | 17103efcb05SHeiko Schocher; SDTIMR2: | SDTIMR2 | 17203efcb05SHeiko Schocher; SDRCR: | SDRCR | 17303efcb05SHeiko Schocher; CLK2XSRC: | CLK2XSRC | 17403efcb05SHeiko Schocher;[ARM_EMIF3DDR_PATCHFXN] 17503efcb05SHeiko Schocher;DDRPHYC1R = 0x000000C2 17603efcb05SHeiko Schocher;SDCR = 0x0017C432 17703efcb05SHeiko Schocher;SDTIMR = 0x26922A09 17803efcb05SHeiko Schocher;SDTIMR2 = 0x4414C722 17903efcb05SHeiko Schocher;SDRCR = 0x00000498 18003efcb05SHeiko Schocher;CLK2XSRC = 0x00000000 18103efcb05SHeiko Schocher 18203efcb05SHeiko Schocher; This section can be used to configure the PLL1 and the EMIF3a registers 18303efcb05SHeiko Schocher; for starting the DDR2 interface on DSP-boot D800K002 devices. 18403efcb05SHeiko Schocher; |------24|------16|-------8|-------0| 18503efcb05SHeiko Schocher; DDRPHYC1R: | DDRPHYC1R | 18603efcb05SHeiko Schocher; SDCR: | SDCR | 18703efcb05SHeiko Schocher; SDTIMR: | SDTIMR | 18803efcb05SHeiko Schocher; SDTIMR2: | SDTIMR2 | 18903efcb05SHeiko Schocher; SDRCR: | SDRCR | 19003efcb05SHeiko Schocher; CLK2XSRC: | CLK2XSRC | 19103efcb05SHeiko Schocher;[DSP_EMIF3DDR_PATCHFXN] 19203efcb05SHeiko Schocher;DDRPHYC1R = 0x000000C4 19303efcb05SHeiko Schocher;SDCR = 0x08134632 19403efcb05SHeiko Schocher;SDTIMR = 0x26922A09 19503efcb05SHeiko Schocher;SDTIMR2 = 0x0014C722 19603efcb05SHeiko Schocher;SDRCR = 0x00000492 19703efcb05SHeiko Schocher;CLK2XSRC = 0x00000000 19803efcb05SHeiko Schocher 19903efcb05SHeiko Schocher;[INPUTFILE] 20003efcb05SHeiko Schocher;FILENAME=u-boot.bin 20103efcb05SHeiko Schocher;LOADADDRESS=0xC1080000 20203efcb05SHeiko Schocher;ENTRYPOINTADDRESS=0xC1080000 203