Home
last modified time | relevance | path

Searched refs:C_O1_I4 (Results 1 – 21 of 21) sorted by relevance

/openbmc/qemu/tcg/s390x/
H A Dtcg-target-con-set.h41 C_O1_I4(v, v, v, vZ, v)
42 C_O1_I4(v, v, v, vZM, v)
43 C_O1_I4(r, r, ri, rI, r)
44 C_O1_I4(r, r, rC, rI, r)
H A Dtcg-target.c.inc3348 return C_O1_I4(r, r, ri, rI, r);
3350 return C_O1_I4(r, r, rC, rI, r);
3420 ? C_O1_I4(v, v, v, vZM, v)
3421 : C_O1_I4(v, v, v, vZ, v));
/openbmc/qemu/tcg/ppc/
H A Dtcg-target-con-set.h36 C_O1_I4(v, v, v, vZM, v)
37 C_O1_I4(r, r, rC, rZ, rZ)
38 C_O1_I4(r, r, r, ri, ri)
H A Dtcg-target.c.inc4264 return C_O1_I4(r, r, rC, rZ, rZ);
4272 return C_O1_I4(r, r, r, ri, ri);
4356 return C_O1_I4(v, v, v, vZM, v);
/openbmc/qemu/tcg/i386/
H A Dtcg-target-con-set.h53 C_O1_I4(x, x, x, xO, x)
54 C_O1_I4(r, r, reT, r, 0)
55 C_O1_I4(r, r, r, ri, ri)
H A Dtcg-target.c.inc3736 return C_O1_I4(r, r, reT, r, 0);
3801 return C_O1_I4(r, r, r, ri, ri);
3868 return C_O1_I4(x, x, x, xO, x);
/openbmc/qemu/tcg/riscv/
H A Dtcg-target-con-set.h22 C_O1_I4(r, r, rI, rM, rM)
32 C_O1_I4(v, v, vL, vK, vK)
H A Dtcg-target.c.inc2700 return C_O1_I4(r, r, rI, rM, rM);
2762 return C_O1_I4(v, v, vL, vK, vK);
/openbmc/qemu/tcg/mips/
H A Dtcg-target-con-set.h29 C_O1_I4(r, rZ, rZ, rZ, 0)
30 C_O1_I4(r, rZ, rZ, rZ, rZ)
H A Dtcg-target.c.inc2255 ? C_O1_I4(r, rZ, rZ, rZ, rZ)
2256 : C_O1_I4(r, rZ, rZ, rZ, 0));
2261 return C_O1_I4(r, rZ, rZ, rZ, rZ);
/openbmc/qemu/tcg/arm/
H A Dtcg-target-con-set.h40 C_O1_I4(r, r, r, rI, rI)
41 C_O1_I4(r, r, rIN, rIK, 0)
H A Dtcg-target.c.inc2187 return C_O1_I4(r, r, rIN, rIK, 0);
2195 return C_O1_I4(r, r, r, rI, rI);
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target-con-set.h18 C_O1_I4(r, rZ, rJ, rI, 0)
H A Dtcg-target.c.inc1610 return C_O1_I4(r, rZ, rJ, rI, 0);
/openbmc/qemu/tcg/tci/
H A Dtcg-target-con-set.h18 C_O1_I4(r, r, r, r, r)
H A Dtcg-target.c.inc157 return C_O1_I4(r, r, r, r, r);
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target-con-set.h40 C_O1_I4(r, rZ, rJ, rZ, rZ)
H A Dtcg-target.c.inc2335 return C_O1_I4(r, rZ, rJ, rZ, rZ);
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target-con-set.h35 C_O1_I4(r, r, rC, rZ, rZ)
H A Dtcg-target.c.inc3072 return C_O1_I4(r, r, rC, rZ, rZ);
/openbmc/qemu/tcg/
H A Dtcg.c654 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4), macro
679 #undef C_O1_I4
699 #define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } }, macro
723 #undef C_O1_I4
743 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4) macro