Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into staging

target/ppc: Fix lxvx/stxvx facility check
linux-user: update syscall_nr.h to Linux v6.10
linux-user: update syscall.tbl

Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into staging

target/ppc: Fix lxvx/stxvx facility check
linux-user: update syscall_nr.h to Linux v6.10
linux-user: update syscall.tbl to Linux v6.11
tcg: Fix iteration step in 32-bit gvec operation
tcg: Propagate new TCGOp to add_as_label_use
tcg/*: Do not expand cmp_vec, cmpsel_vec early
tcg/optimize: Fold movcond with true and false values identical
tcg/optimize: Optimize cmp_vec and cmpsel_vec
tcg/optimize: Optimize bitsel_vec
tcg/i386: Optimize cmpsel with constant 0 operand 3.
tcg/i386: Implement cmp_vec with avx512 insns
tcg/i386: Implement cmpsel_vec with avx512 insns
tcg/i386: Implement vector TST{EQ,NE} for avx512
tcg/ppc: Implement cmpsel_vec and optimize with constant 0/-1 arguments
tcg/s390x: Implement cmpsel_vec and optimize with constant 0/-1 arguments

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# gpg: Signature made Sun 22 Sep 2024 13:00:02 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu: (31 commits)
linux-user: update syscall.tbl to Linux v6.11
linux-user,loongarch: move to syscalltbl file
linux-user,hexagon: move to syscalltbl file
linux-user,riscv: move to syscalltbl file
linux-user,openrisc: move to syscalltbl file
linux-user,aarch64: move to syscalltbl file
linux-user: update syscall.tbl to Linux v6.10
linux-user, mips: update syscall-args-o32.c.inc to Linux v6.10
linux-user: update syscall_nr.h to Linux v6.10
target/ppc: Fix lxvx/stxvx facility check
tcg/s390x: Optimize cmpsel with constant 0/-1 arguments
tcg/s390x: Implement cmpsel_vec
tcg/ppc: Optimize cmpsel with constant 0/-1 arguments
tcg/ppc: Implement cmpsel_vec
tcg/i386: Implement vector TST{EQ,NE} for avx512
tcg/i386: Implement cmpsel_vec with avx512 insns
tcg/i386: Add predicate parameters to tcg_out_evex_opc
tcg/i386: Implement cmp_vec with avx512 insns
tcg/i386: Optimize cmpsel with constant 0 operand 3.
tcg/optimize: Optimize bitsel_vec
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg/ppc: Optimize cmpsel with constant 0/-1 arguments

These can be simplified to and/or/andc/orc,
avoiding the load of the constantinto a register.

Signed-off-by: Richard Henderson <richard.henders

tcg/ppc: Optimize cmpsel with constant 0/-1 arguments

These can be simplified to and/or/andc/orc,
avoiding the load of the constantinto a register.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg/ppc: Implement cmpsel_vec

Do not allow cmpsel_vec to be expanded early, so that we can
make the correct decision wrt the sense of the comparison.

Signed-off-by: Richard Henderson <richard.hende

tcg/ppc: Implement cmpsel_vec

Do not allow cmpsel_vec to be expanded early, so that we can
make the correct decision wrt the sense of the comparison.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu into staging

tcg: Introduce TCG_COND_TST{EQ,NE}
target/alpha: Use TCG_COND_TST{EQ,NE}
target/m68k: Use TCG_COND_TST{EQ,NE} in gen_f

Merge tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu into staging

tcg: Introduce TCG_COND_TST{EQ,NE}
target/alpha: Use TCG_COND_TST{EQ,NE}
target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc
target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}
target/s390x: Improve general case of disas_jcc

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# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu: (39 commits)
tcg/tci: Support TCG_COND_TST{EQ,NE}
tcg/s390x: Support TCG_COND_TST{EQ,NE}
tcg/s390x: Add TCG_CT_CONST_CMP
tcg/s390x: Split constraint A into J+U
tcg/ppc: Support TCG_COND_TST{EQ,NE}
tcg/ppc: Add TCG_CT_CONST_CMP
tcg/ppc: Tidy up tcg_target_const_match
tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel
tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc
tcg/sparc64: Support TCG_COND_TST{EQ,NE}
tcg/sparc64: Pass TCGCond to tcg_out_cmp
tcg/sparc64: Hoist read of tcg_cond_to_rcond
tcg/i386: Use TEST r,r to test 8/16/32 bits
tcg/i386: Improve TSTNE/TESTEQ vs powers of two
tcg/i386: Support TCG_COND_TST{EQ,NE}
tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp
tcg/i386: Pass x86 condition codes to tcg_out_cmov
tcg/arm: Support TCG_COND_TST{EQ,NE}
tcg/arm: Split out tcg_out_cmp()
tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg/ppc: Add TCG_CT_CONST_CMP

Better constraint for tcg_out_cmp, based on the comparison.
We can't yet remove the fallback to load constants into a
scratch because of tcg_out_cmp2, but that path sho

tcg/ppc: Add TCG_CT_CONST_CMP

Better constraint for tcg_out_cmp, based on the comparison.
We can't yet remove the fallback to load constants into a
scratch because of tcg_out_cmp2, but that path should not
be as frequent.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg/ppc: Use new registers for LQ destination

LQ has a constraint that RTp != RA, else SIGILL.
Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a
new register pair, so that it cannot

tcg/ppc: Use new registers for LQ destination

LQ has a constraint that RTp != RA, else SIGILL.
Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a
new register pair, so that it cannot overlap the input address.

This requires new support in process_op_defs and tcg_reg_alloc_op.

Cc: qemu-stable@nongnu.org
Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240102013456.131846-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
(cherry picked from commit ca5bed07d0e7e0530c2cafbc134c4f74e582ac50)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>

show more ...

Merge tag 'pull-tcg-20240111' of https://gitlab.com/rth7680/qemu into staging

tcg/i386: Use more 8-bit immediate forms for add, sub, or, xor
tcg/ppc: Use new registers for LQ destination
util: fix b

Merge tag 'pull-tcg-20240111' of https://gitlab.com/rth7680/qemu into staging

tcg/i386: Use more 8-bit immediate forms for add, sub, or, xor
tcg/ppc: Use new registers for LQ destination
util: fix build with musl libc on ppc64le

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# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20240111' of https://gitlab.com/rth7680/qemu:
util: fix build with musl libc on ppc64le
tcg/ppc: Use new registers for LQ destination
tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates
tcg/i386: convert add/sub of 128 to sub/add of -128

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg/ppc: Use new registers for LQ destination

LQ has a constraint that RTp != RA, else SIGILL.
Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a
new register pair, so that it cannot

tcg/ppc: Use new registers for LQ destination

LQ has a constraint that RTp != RA, else SIGILL.
Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a
new register pair, so that it cannot overlap the input address.

This requires new support in process_op_defs and tcg_reg_alloc_op.

Cc: qemu-stable@nongnu.org
Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240102013456.131846-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20230530' of https://gitlab.com/rth7680/qemu into staging

Improvements to 128-bit atomics:
- Separate __int128_t type and arithmetic detection
- Support 128-bit load/store in

Merge tag 'pull-tcg-20230530' of https://gitlab.com/rth7680/qemu into staging

Improvements to 128-bit atomics:
- Separate __int128_t type and arithmetic detection
- Support 128-bit load/store in backend for i386, aarch64, ppc64, s390x
- Accelerate atomics via host/include/
Decodetree:
- Add named field syntax
- Move tests to meson

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# gpg: Signature made Tue 30 May 2023 11:58:37 AM PDT
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# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-tcg-20230530' of https://gitlab.com/rth7680/qemu: (27 commits)
tests/decode: Add tests for various named-field cases
scripts/decodetree: Implement named field support
scripts/decodetree: Implement a topological sort
scripts/decodetree: Pass lvalue-formatter function to str_extract()
docs: Document decodetree named field syntax
tests/decode: Convert tests to meson
decodetree: Do not remove output_file from /dev
decodetree: Diagnose empty pattern group
decodetree: Fix recursion in prop_format and build_tree
decodetree: Add --test-for-error
tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITS
accel/tcg: Add aarch64 store_atom_insert_al16
accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_al8
accel/tcg: Add x86_64 load_atom_extract_al16_or_al8
accel/tcg: Extract store_atom_insert_al16 to host header
accel/tcg: Extract load_atom_extract_al16_or_al8 to host header
tcg/s390x: Support 128-bit load/store
tcg/ppc: Support 128-bit load/store
tcg/aarch64: Support 128-bit load/store
tcg/aarch64: Simplify constraints on qemu_ld/st
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg/ppc: Support 128-bit load/store

Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required.
Note that these instructions do not require 16-byte alignment.

Reviewed-by: Daniel Henrique Barboza

tcg/ppc: Support 128-bit load/store

Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required.
Note that these instructions do not require 16-byte alignment.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20230511-2' of https://gitlab.com/rth7680/qemu into staging

target/m68k: Fix gen_load_fp regression
accel/tcg: Ensure fairness with icount
disas: Move disas.c into the target-ind

Merge tag 'pull-tcg-20230511-2' of https://gitlab.com/rth7680/qemu into staging

target/m68k: Fix gen_load_fp regression
accel/tcg: Ensure fairness with icount
disas: Move disas.c into the target-independent source sets
tcg: Use common routines for calling slow path helpers
tcg/*: Cleanups to qemu_ld/st constraints
tcg: Remove TARGET_ALIGNED_ONLY
accel/tcg: Reorg system mode load/store helpers

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# gpg: Signature made Thu 11 May 2023 11:43:34 AM BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-tcg-20230511-2' of https://gitlab.com/rth7680/qemu: (53 commits)
target/loongarch: Do not include tcg-ldst.h
accel/tcg: Reorg system mode store helpers
accel/tcg: Reorg system mode load helpers
accel/tcg: Introduce tlb_read_idx
accel/tcg: Add cpu_in_serial_context
tcg: Remove TARGET_ALIGNED_ONLY
target/sh4: Remove TARGET_ALIGNED_ONLY
target/sh4: Use MO_ALIGN where required
target/nios2: Remove TARGET_ALIGNED_ONLY
target/mips: Remove TARGET_ALIGNED_ONLY
target/mips: Use MO_ALIGN instead of 0
target/mips: Add missing default_tcg_memop_mask
target/mips: Add MO_ALIGN to gen_llwp, gen_scwp
tcg/s390x: Simplify constraints on qemu_ld/st
tcg/s390x: Use ALGFR in constructing softmmu host address
tcg/riscv: Simplify constraints on qemu_ld/st
tcg/ppc: Remove unused constraint J
tcg/ppc: Remove unused constraints A, B, C, D
tcg/ppc: Adjust constraints on qemu_ld/st
tcg/ppc: Reorg tcg_out_tlb_read
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg/ppc: Adjust constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally
available registers. Now that we handle overlap betwen inputs and
helper arguments, we

tcg/ppc: Adjust constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally
available registers. Now that we handle overlap betwen inputs and
helper arguments, we can allow any allocatable reg.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210202' into staging

TCG backend constraints cleanup

# gpg: Signature made Tue 02 Feb 2021 22:59:19 GMT
# gpg: using

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210202' into staging

TCG backend constraints cleanup

# gpg: Signature made Tue 02 Feb 2021 22:59:19 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20210202: (24 commits)
tcg: Remove TCG_TARGET_CON_SET_H
tcg/tci: Split out constraint sets to tcg-target-con-set.h
tcg/sparc: Split out constraint sets to tcg-target-con-set.h
tcg/s390: Split out constraint sets to tcg-target-con-set.h
tcg/riscv: Split out constraint sets to tcg-target-con-set.h
tcg/ppc: Split out constraint sets to tcg-target-con-set.h
tcg/mips: Split out constraint sets to tcg-target-con-set.h
tcg/arm: Split out constraint sets to tcg-target-con-set.h
tcg/aarch64: Split out constraint sets to tcg-target-con-set.h
tcg/i386: Split out constraint sets to tcg-target-con-set.h
tcg: Remove TCG_TARGET_CON_STR_H
tcg/sparc: Split out target constraints to tcg-target-con-str.h
tcg/s390: Split out target constraints to tcg-target-con-str.h
tcg/riscv: Split out target constraints to tcg-target-con-str.h
tcg/mips: Split out target constraints to tcg-target-con-str.h
tcg/tci: Split out target constraints to tcg-target-con-str.h
tcg/ppc: Split out target constraints to tcg-target-con-str.h
tcg/aarch64: Split out target constraints to tcg-target-con-str.h
tcg/arm: Split out target constraints to tcg-target-con-str.h
tcg/i386: Split out target constraints to tcg-target-con-str.h
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg/ppc: Split out constraint sets to tcg-target-con-set.h

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>