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Searched refs:C_O0_I2 (Results 1 – 21 of 21) sorted by relevance

/openbmc/qemu/tcg/i386/
H A Dtcg-target-con-set.h19 C_O0_I2(L, L)
20 C_O0_I2(qi, r)
21 C_O0_I2(re, r)
22 C_O0_I2(ri, r)
23 C_O0_I2(r, reT)
24 C_O0_I2(s, L)
25 C_O0_I2(x, r)
H A Dtcg-target.c.inc3635 return C_O0_I2(qi, r);
3641 return C_O0_I2(ri, r);
3644 return C_O0_I2(re, r);
3684 return C_O0_I2(r, reT);
3770 return C_O0_I2(L, L);
3772 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I3(L, L, L);
3774 return C_O0_I2(s, L);
3776 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(s, L) : C_O0_I3(s, L, L);
3784 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I3(L, L, L);
3786 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I4(L, L, L, L);
[all …]
/openbmc/qemu/tcg/s390x/
H A Dtcg-target-con-set.h16 C_O0_I2(r, r)
17 C_O0_I2(r, ri)
18 C_O0_I2(r, rC)
19 C_O0_I2(v, r)
H A Dtcg-target.c.inc3231 return C_O0_I2(r, r);
3295 return C_O0_I2(r, ri);
3297 return C_O0_I2(r, rC);
3335 return C_O0_I2(r, r);
3372 return C_O0_I2(v, r);
/openbmc/qemu/tcg/arm/
H A Dtcg-target-con-set.h13 C_O0_I2(r, r)
14 C_O0_I2(r, rIN)
15 C_O0_I2(q, q)
16 C_O0_I2(w, r)
H A Dtcg-target.c.inc2146 return C_O0_I2(r, r);
2181 return C_O0_I2(r, rIN);
2206 return C_O0_I2(q, q);
2215 return C_O0_I2(w, r);
/openbmc/qemu/tcg/riscv/
H A Dtcg-target-con-set.h13 C_O0_I2(rZ, r)
14 C_O0_I2(rZ, rZ)
24 C_O0_I2(v, r)
H A Dtcg-target.c.inc2632 return C_O0_I2(rZ, r);
2696 return C_O0_I2(rZ, rZ);
2717 return C_O0_I2(rZ, r);
2720 return C_O0_I2(v, r);
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target-con-set.h18 C_O0_I2(rZ, r)
19 C_O0_I2(rZ, rZ)
20 C_O0_I2(w, r)
H A Dtcg-target.c.inc2203 return C_O0_I2(rZ, r);
2215 return C_O0_I2(rZ, rZ);
2343 return C_O0_I2(w, r);
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target-con-set.h13 C_O0_I2(r, rC)
14 C_O0_I2(rZ, r)
15 C_O0_I2(w, r)
H A Dtcg-target.c.inc3006 return C_O0_I2(rZ, r);
3068 return C_O0_I2(r, rC);
3086 return C_O0_I2(rZ, r);
3133 return C_O0_I2(w, r);
/openbmc/qemu/tcg/ppc/
H A Dtcg-target-con-set.h13 C_O0_I2(r, r)
14 C_O0_I2(r, rC)
15 C_O0_I2(v, r)
H A Dtcg-target.c.inc4192 return C_O0_I2(r, r);
4256 return C_O0_I2(r, rC);
4290 return C_O0_I2(r, r);
4292 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r);
4294 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r);
4296 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I4(r, r, r, r);
4350 return C_O0_I2(v, r);
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target-con-set.h13 C_O0_I2(rZ, r)
14 C_O0_I2(rZ, rJ)
H A Dtcg-target.c.inc1571 return C_O0_I2(rZ, r);
1607 return C_O0_I2(rZ, rJ);
/openbmc/qemu/tcg/mips/
H A Dtcg-target-con-set.h13 C_O0_I2(rZ, r)
14 C_O0_I2(rZ, rZ)
H A Dtcg-target.c.inc2191 return C_O0_I2(rZ, r);
2251 return C_O0_I2(rZ, rZ);
2270 return C_O0_I2(rZ, r);
2272 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r);
2278 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r);
2280 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r)
/openbmc/qemu/tcg/tci/
H A Dtcg-target-con-set.h13 C_O0_I2(r, r)
H A Dtcg-target.c.inc81 return C_O0_I2(r, r);
135 return C_O0_I2(r, r);
168 return C_O0_I2(r, r);
170 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r);
172 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r);
174 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I4(r, r, r, r);
/openbmc/qemu/tcg/
H A Dtcg.c647 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2), macro
673 #undef C_O0_I2
692 #define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } }, macro
717 #undef C_O0_I2
736 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2) macro