Searched refs:CTRL2 (Results 1 – 5 of 5) sorted by relevance
/openbmc/qemu/hw/dma/ |
H A D | xlnx_csu_dma.c | 95 REG32(CTRL2, 0x24) 96 FIELD(CTRL2, ARCACHE, 24, 3) /* rw */ 97 FIELD(CTRL2, ROUTE_BIT, 23, 1) /* rw */ 98 FIELD(CTRL2, TIMEOUT_EN, 22, 1) /* rw */ 99 FIELD(CTRL2, TIMEOUT_PRE, 4, 12) /* rw, reset: 0xFFF */ 100 FIELD(CTRL2, MAX_OUTS_CMDS, 0, 4) /* rw, reset: 0x8 */ 316 uint32_t div = ARRAY_FIELD_EX32(s->regs, CTRL2, TIMEOUT_PRE) + 1; in xlnx_csu_dma_src_notify()
|
/openbmc/linux/sound/soc/codecs/ |
H A D | ak4613.c | 114 #define CTRL2 0x04 /* Control 2 */ macro 643 snd_soc_component_update_bits(component, CTRL2, DFS_MASK, ctrl2); in ak4613_dai_hw_params()
|
/openbmc/linux/drivers/net/ethernet/amd/ |
H A D | amd8111e.h | 52 #define CTRL2 0x70 /* Control2 register */ macro
|
H A D | amd8111e.c | 435 writel((u32)XPHYANE | XPHYRST, mmio + CTRL2); in amd8111e_restart()
|
/openbmc/linux/drivers/media/i2c/ |
H A D | ov2640.c | 70 #define CTRL2 0x86 /* DSP Module enable 2 */ macro 508 { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
|