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Searched refs:CSR_UPMBASE (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h506 #define CSR_UPMBASE 0x4c2 macro
H A Dcpu.c797 CSR_UPMBASE, in riscv_cpu_dump_state()
H A Dcsr.c5323 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase,