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Searched refs:CSR_TDATA3 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h253 #define CSR_TDATA3 0x7a3 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h360 #define CSR_TDATA3 0x7a3 macro
H A Dcsr.c5315 [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },