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Searched refs:CSR_SSTATUS (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/arch/riscv/kvm/
H A Dvcpu_switch.S52 csrrw t0, CSR_SSTATUS, t0
175 csrrw t5, CSR_SSTATUS, t5
240 csrr t2, CSR_SSTATUS
242 csrs CSR_SSTATUS, t1
277 csrw CSR_SSTATUS, t2
283 csrr t2, CSR_SSTATUS
285 csrs CSR_SSTATUS, t1
320 csrw CSR_SSTATUS, t2
326 csrr t2, CSR_SSTATUS
329 csrs CSR_SSTATUS, t1
[all …]
/openbmc/linux/arch/riscv/include/asm/
H A Dvector.h58 csr_set(CSR_SSTATUS, SR_VS); in riscv_v_enable()
63 csr_clear(CSR_SSTATUS, SR_VS); in riscv_v_disable()
H A Dcsr.h274 #define CSR_SSTATUS 0x100 macro
423 # define CSR_STATUS CSR_SSTATUS
/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h175 #define CSR_SSTATUS 0x100 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h192 #define CSR_SSTATUS 0x100 macro
H A Dcsr.c5158 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus,