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Searched refs:CSR_PMPADDR5 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h238 #define CSR_PMPADDR5 0x3b5 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h344 #define CSR_PMPADDR5 0x3b5 macro
H A Dcsr.c5299 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr },