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Searched refs:CSR_MTINST (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h278 #define CSR_MTINST 0x34a macro
H A Dcsr.c5253 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst,