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Searched refs:CSR_MSTATEEN3 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h315 #define CSR_MSTATEEN3 0x30F macro
H A Dcsr.c5116 [CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen,