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Searched refs:CSR_MSTATEEN0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h309 #define CSR_MSTATEEN0 0x30C macro
H A Dcsr.c2545 *val = env->mstateen[csrno - CSR_MSTATEEN0]; in read_mstateen()
2555 reg = &env->mstateen[csrno - CSR_MSTATEEN0]; in write_mstateen()
5099 [CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0,