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Searched refs:CSR_MHPMEVENT28 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h220 #define CSR_MHPMEVENT28 0x33c macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h432 #define CSR_MHPMEVENT28 0x33c macro
H A Dcsr.c5489 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_mhpmevent,