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Searched refs:CSR_MHPMEVENT15H (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h452 #define CSR_MHPMEVENT15H 0x72f macro
H A Dcsr.c5541 [CSR_MHPMEVENT15H] = { "mhpmevent15h", sscofpmf_32, read_mhpmeventh,