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Searched refs:CSR_MENVCFGH (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/arch/riscv/include/asm/
H A Dcsr.h359 #define CSR_MENVCFGH 0x31a
358 #define CSR_MENVCFGH global() macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h306 #define CSR_MENVCFGH 0x31A macro
H A Dcsr.c5089 [CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh,