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Searched refs:CSR_MEDELEGH (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h162 #define CSR_MEDELEGH 0x312 macro
H A Dcsr.c5054 [CSR_MEDELEGH] = { "medelegh", any32, read_zero, write_ignore,