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Searched refs:CSR_MCYCLEH (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h289 #define CSR_MCYCLEH 0xb80 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h141 #define CSR_MCYCLEH 0xb80 macro
H A Dcsr.c214 if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) { in mctr()
1138 int ctr_idx = csrno - CSR_MCYCLEH; in write_mhpmcounterh()
1214 if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) { in read_hpmcounterh()
1215 ctr_index = csrno - CSR_MCYCLEH; in read_hpmcounterh()
5027 [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh,