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Searched refs:CSR_HENVCFGH (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/arch/riscv/include/asm/
H A Dcsr.h322 #define CSR_HENVCFGH 0x61a
321 #define CSR_HENVCFGH global() macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h251 #define CSR_HENVCFGH 0x61A macro
H A Dcsr.c5095 [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh,
/openbmc/linux/arch/riscv/kvm/
H A Dvcpu.c514 csr_write(CSR_HENVCFGH, henvcfg >> 32); in kvm_riscv_vcpu_update_config()