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Searched refs:CSR_FCSR (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/linux-user/riscv/
H A Dsignal.c93 uint32_t fcsr = riscv_csr_read(env, CSR_FCSR); in setup_sigcontext()
162 riscv_csr_write(env, CSR_FCSR, fcsr); in restore_sigcontext()
/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h173 #define CSR_FCSR 0x3 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h55 #define CSR_FCSR 0x003 macro
H A Dcpu.c831 RISCVException res = riscv_csrrw_debug(env, CSR_FCSR, &val, 0, 0); in riscv_cpu_dump_state()
834 csr_ops[CSR_FCSR].name, val); in riscv_cpu_dump_state()
H A Dcsr.c4990 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },