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Searched refs:CSR_CYCLE (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/arch/riscv/include/asm/
H A Dkvm_vcpu_pmu.h62 {.base = CSR_CYCLE, .count = 32, .func = kvm_riscv_vcpu_pmu_read_hpm },
65 {.base = CSR_CYCLE, .count = 32, .func = kvm_riscv_vcpu_pmu_read_hpm },
100 if (csr_num == CSR_CYCLE || csr_num == CSR_INSTRET) { in kvm_riscv_vcpu_pmu_read_legacy()
109 {.base = CSR_CYCLE, .count = 3, .func = kvm_riscv_vcpu_pmu_read_legacy },
H A Dcsr.h207 #define CSR_CYCLE 0xc00 macro
/openbmc/linux/tools/lib/perf/
H A Dmmap.c400 #define CSR_CYCLE 0xc00 macro
437 switchcase_csr_read_32(CSR_CYCLE, ret) in csr_read_num()
453 return csr_read_num(CSR_CYCLE + counter); in read_perf_counter()
/openbmc/linux/arch/riscv/kvm/
H A Dvcpu_pmu.c293 if (csr_num == CSR_CYCLE || csr_num == CSR_INSTRET) { in kvm_riscv_vcpu_pmu_read_hpm()
305 cidx = csr_num - CSR_CYCLE; in kvm_riscv_vcpu_pmu_read_hpm()
601 pmc->cinfo.csr = CSR_CYCLE + i; in kvm_riscv_vcpu_pmu_init()
/openbmc/linux/drivers/perf/
H A Driscv_pmu.c118 switchcase_csr_read_32(CSR_CYCLE, ret) in csr_read_num()
138 if (csr < CSR_CYCLE || csr > CSR_HPMCOUNTER31H || in riscv_pmu_ctr_read_csr()
H A Driscv_pmu_legacy.c53 val = riscv_pmu_ctr_read_csr(CSR_CYCLE); in pmu_legacy_read_ctr()
H A Driscv_pmu_sbi.c302 if (!hpm_width && info->csr != CSR_CYCLE && info->csr != CSR_INSTRET) in riscv_pmu_get_hpm_info()
317 return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE; in pmu_sbi_csr_index()
364 cmask = 1UL << (CSR_INSTRET - CSR_CYCLE); in pmu_sbi_ctr_get_idx()
732 hidx = info->csr - CSR_CYCLE; in pmu_sbi_ovf_handler()
/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h321 #define CSR_CYCLE 0xc00 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h73 #define CSR_CYCLE 0xc00 macro
H A Dcsr.c112 int base_csrno = CSR_CYCLE; in ctr()
122 if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) || in ctr()
1200 } else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) { in read_hpmcounter()
1201 ctr_index = csrno - CSR_CYCLE; in read_hpmcounter()
5000 [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter },