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Searched refs:CSI (Results 1 – 25 of 83) sorted by relevance

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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dti,omap3isp.txt14 CSI PHYs and receivers registers.
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
42 vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1
43 vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2
48 lane-polarities : lane polarity (required on CSI-2)
51 be either 1 or 2. (required on CSI-2)
52 clock-lanes : the clock lane (from 1 to 3). (required on CSI-2)
H A Dimx.txt27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
39 - clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx
46 connecting with a MIPI CSI-2 source, and ports 1
49 MIPI CSI-2 virtual channel outputs.
H A Dcdns,csi2tx.txt4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
5 4 CSI lanes in output, and up to 4 different pixel streams in input.
30 0 CSI-2 output
/openbmc/linux/drivers/media/platform/nxp/
H A DKconfig8 tristate "NXP CSI Bridge driver"
17 Driver for the NXP Camera Sensor Interface (CSI) Bridge. This device
21 tristate "NXP i.MX8MQ MIPI CSI-2 receiver"
28 Video4Linux2 driver for the MIPI CSI-2 receiver found on the i.MX8MQ
32 tristate "NXP MIPI CSI-2 CSIS receiver found on i.MX7 and i.MX8 models"
39 Video4Linux2 sub-device driver for the MIPI CSI-2 CSIS receiver
/openbmc/linux/Documentation/admin-guide/media/
H A Dimx7.rst14 - CMOS Sensor Interface (CSI)
16 - MIPI CSI-2 Receiver
20 MIPI Camera Input ---> MIPI CSI-2 --- > |\
24 | U | ------> CSI ---> Capture
39 This is the MIPI CSI-2 receiver entity. It has one sink pad to receive the pixel
40 data from MIPI CSI-2 camera sensor. It has one source pad, corresponding to the
48 sensor with a parallel interface or from MIPI CSI-2 virtual channel 0. It has
49 a single source pad that routes to the CSI.
54 The CSI enables the chip to connect directly to external CMOS image sensor. CSI
55 can interface directly with Parallel and MIPI CSI-2 buses. It has 256 x 64 FIFO
[all …]
H A Dimx.rst16 - Camera Serial Interface (CSI)
31 The CSI is the backend capture unit that interfaces directly with
32 camera sensors over Parallel, BT.656/1120, and MIPI CSI-2 buses.
66 - MIPI CSI-2 Receiver for camera sensors with the MIPI CSI-2 bus
69 to send to a CSI.
84 - Supports parallel, BT.565, and MIPI CSI-2 interfaces.
98 CSI. There is also support in the future for sending frames to the
112 The i.MX5/6 topologies can differ upstream from the IPUv3 CSI video
115 MIPI CSI-2 OV5640 sensor, requires the i.MX6 MIPI CSI-2 receiver. But
117 therefore does not require the MIPI CSI-2 receiver, so it is missing in
[all …]
/openbmc/linux/drivers/media/platform/xilinx/
H A DKconfig18 tristate "Xilinx CSI-2 Rx Subsystem"
20 Driver for Xilinx MIPI CSI-2 Rx Subsystem. This is a V4L sub-device
21 based driver that takes input from CSI-2 Tx source and converts
/openbmc/linux/Documentation/driver-api/media/
H A Dtx-rx.rst9 these devices include a camera sensor, a TV tuner and a parallel or a CSI-2
17 MIPI CSI-2
20 CSI-2 is a data bus intended for transferring images from cameras to
58 CSI-2 transmitter drivers
78 - Number of data lanes used on the CSI-2 link. This can
96 As part of transitioning to high speed mode, a CSI-2 transmitter typically
118 In the context of CSI-2, the ``.pre_streamon()`` callback is used to transition
/openbmc/linux/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
H A DKconfig3 tristate "Allwinner A83T MIPI CSI-2 Controller and D-PHY Driver"
14 Support for the Allwinner A83T MIPI CSI-2 controller and D-PHY.
/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dtc358743.txt4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
20 MIPI CSI-2 clock is continuous or non-continuous.
25 For further information on the MIPI CSI-2 endpoint node properties, see
/openbmc/linux/drivers/media/platform/sunxi/sun6i-mipi-csi2/
H A DKconfig3 tristate "Allwinner A31 MIPI CSI-2 Controller Driver"
14 Support for the Allwinner A31 MIPI CSI-2 controller, also found on
/openbmc/linux/drivers/media/platform/sunxi/sun6i-csi/
H A DKconfig3 tristate "Allwinner A31 Camera Sensor Interface (CSI) Driver"
13 Support for the Allwinner A31 Camera Sensor Interface (CSI)
/openbmc/linux/drivers/media/pci/intel/ipu3/
H A DKconfig14 This is the Intel IPU3 CIO2 CSI-2 receiver unit, found in Intel
18 Say Y or M here if you have a Skylake/Kaby Lake SoC with MIPI CSI-2
/openbmc/linux/drivers/media/platform/renesas/rzg2l-cru/
H A DKconfig4 tristate "RZ/G2L MIPI CSI-2 Receiver"
13 Support for Renesas RZ/G2L (and alike SoC's) MIPI CSI-2
/openbmc/linux/drivers/media/platform/renesas/rcar-vin/
H A DKconfig3 tristate "R-Car MIPI CSI-2 Receiver"
12 Support for Renesas R-Car MIPI CSI-2 receiver.
/openbmc/linux/Documentation/driver-api/media/drivers/
H A Drkisp1.rst31 - V12 supports a new CSI-host implementation but can still
43 - V13 does not support the old CSI-host implementation anymore
/openbmc/u-boot/arch/arm/mach-rockchip/rk3399/
H A DKconfig28 * HDMI, eDP, MIPI-DSI, MIPI-DSI/CSI and MIPI-CSI
/openbmc/linux/drivers/media/platform/sunxi/sun4i-csi/
H A DKconfig13 This is a V4L2 driver for the Allwinner A10 CSI
/openbmc/linux/drivers/media/pci/intel/ivsc/
H A DKconfig14 camera sensor ownership and CSI-2 link through Image Processing
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g054l2-smarc-cru-csi-ov5645.dtso4 * connected to CSI and CRU enabled.
H A Dr9a07g044c2-smarc-cru-csi-ov5645.dtso4 * OV5645 camera connected to CSI and CRU enabled.
H A Dr9a07g044l2-smarc-cru-csi-ov5645.dtso4 * connected to CSI and CRU enabled.
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-a311d-bananapi-m2s.dts21 /* Camera (CSI) bus */
/openbmc/linux/drivers/phy/rockchip/
H A DKconfig52 tristate "Rockchip Innosilicon MIPI CSI PHY driver"
57 Enable this to support the Rockchip MIPI CSI PHY with
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c125 MBUS_CONF( CSI, true, HIGHEST, 0, 256, 128, 32); in mctl_set_master_priority_h3()
150 MBUS_CONF( CSI, true, HIGH, 0, 256, 128, 0); in mctl_set_master_priority_a64()
180 MBUS_CONF( CSI, true, HIGHEST, 0, 150, 120, 100); in mctl_set_master_priority_h5()
208 MBUS_CONF( CSI, true, HIGHEST, 0, 150, 120, 100); in mctl_set_master_priority_r40()

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