1*7eec52dbSSakari AilusOMAP 3 ISP Device Tree bindings 2*7eec52dbSSakari Ailus=============================== 3*7eec52dbSSakari Ailus 4*7eec52dbSSakari AilusThe DT definitions can be found in include/dt-bindings/media/omap3-isp.h. 5*7eec52dbSSakari Ailus 6*7eec52dbSSakari AilusRequired properties 7*7eec52dbSSakari Ailus=================== 8*7eec52dbSSakari Ailus 9*7eec52dbSSakari Ailuscompatible : must contain "ti,omap3-isp" 10*7eec52dbSSakari Ailus 11*7eec52dbSSakari Ailusreg : the two registers sets (physical address and length) for the 12*7eec52dbSSakari Ailus ISP. The first set contains the core ISP registers up to 13*7eec52dbSSakari Ailus the end of the SBL block. The second set contains the 14*7eec52dbSSakari Ailus CSI PHYs and receivers registers. 15*7eec52dbSSakari Ailusinterrupts : the ISP interrupt specifier 16*7eec52dbSSakari Ailusiommus : phandle and IOMMU specifier for the IOMMU that serves the ISP 17*7eec52dbSSakari Ailussyscon : the phandle and register offset to the Complex I/O or CSI-PHY 18*7eec52dbSSakari Ailus register 19*7eec52dbSSakari Ailusti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430) 20*7eec52dbSSakari Ailus 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630) 21*7eec52dbSSakari Ailus#clock-cells : Must be 1 --- the ISP provides two external clocks, 22*7eec52dbSSakari Ailus cam_xclka and cam_xclkb, at indices 0 and 1, 23*7eec52dbSSakari Ailus respectively. Please find more information on common 24*7eec52dbSSakari Ailus clock bindings in ../clock/clock-bindings.txt. 25*7eec52dbSSakari Ailus 26*7eec52dbSSakari AilusPort nodes (optional) 27*7eec52dbSSakari Ailus--------------------- 28*7eec52dbSSakari Ailus 29*7eec52dbSSakari AilusMore documentation on these bindings is available in 30*7eec52dbSSakari Ailusvideo-interfaces.txt in the same directory. 31*7eec52dbSSakari Ailus 32*7eec52dbSSakari Ailusreg : The interface: 33*7eec52dbSSakari Ailus 0 - parallel (CCDC) 34*7eec52dbSSakari Ailus 1 - CSIPHY1 -- CSI2C / CCP2B on 3630; 35*7eec52dbSSakari Ailus CSI1 -- CSIb on 3430 36*7eec52dbSSakari Ailus 2 - CSIPHY2 -- CSI2A / CCP2B on 3630; 37*7eec52dbSSakari Ailus CSI2 -- CSIa on 3430 38*7eec52dbSSakari Ailus 39*7eec52dbSSakari AilusOptional properties 40*7eec52dbSSakari Ailus=================== 41*7eec52dbSSakari Ailus 42*7eec52dbSSakari Ailusvdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1 43*7eec52dbSSakari Ailusvdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2 44*7eec52dbSSakari Ailus 45*7eec52dbSSakari AilusEndpoint nodes 46*7eec52dbSSakari Ailus-------------- 47*7eec52dbSSakari Ailus 48*7eec52dbSSakari Ailuslane-polarities : lane polarity (required on CSI-2) 49*7eec52dbSSakari Ailus 0 -- not inverted; 1 -- inverted 50*7eec52dbSSakari Ailusdata-lanes : an array of data lanes from 1 to 3. The length can 51*7eec52dbSSakari Ailus be either 1 or 2. (required on CSI-2) 52*7eec52dbSSakari Ailusclock-lanes : the clock lane (from 1 to 3). (required on CSI-2) 53*7eec52dbSSakari Ailus 54*7eec52dbSSakari Ailus 55*7eec52dbSSakari AilusExample 56*7eec52dbSSakari Ailus======= 57*7eec52dbSSakari Ailus 58*7eec52dbSSakari Ailus isp@480bc000 { 59*7eec52dbSSakari Ailus compatible = "ti,omap3-isp"; 60*7eec52dbSSakari Ailus reg = <0x480bc000 0x12fc 61*7eec52dbSSakari Ailus 0x480bd800 0x0600>; 62*7eec52dbSSakari Ailus interrupts = <24>; 63*7eec52dbSSakari Ailus iommus = <&mmu_isp>; 64*7eec52dbSSakari Ailus syscon = <&scm_conf 0x2f0>; 65*7eec52dbSSakari Ailus ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>; 66*7eec52dbSSakari Ailus #clock-cells = <1>; 67*7eec52dbSSakari Ailus ports { 68*7eec52dbSSakari Ailus #address-cells = <1>; 69*7eec52dbSSakari Ailus #size-cells = <0>; 70*7eec52dbSSakari Ailus }; 71*7eec52dbSSakari Ailus }; 72