Searched refs:CSCR (Results 1 – 8 of 8) sorted by relevance
| /openbmc/u-boot/arch/arm/cpu/arm920t/imx/ |
| H A D | speed.c | 53 return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK(); in get_FCLK()
59 u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1; in get_HCLK()
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| /openbmc/u-boot/board/armadeus/apf27/ |
| H A D | lowlevel_init.S | 31 ldr r0, =CSCR
43 write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
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| /openbmc/linux/drivers/net/ethernet/realtek/ |
| H A D | 8139too.c | 327 CSCR = 0x74, /* Chip Status and Configuration Register. */ enumerator
1494 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) { in rtl8139_tune_twister()
1496 RTL_W16 (CSCR, CSCR_LinkDownOffCmd); in rtl8139_tune_twister()
1501 RTL_W16 (CSCR, CSCR_LinkDownCmd); in rtl8139_tune_twister()
1510 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits; in rtl8139_tune_twister()
1539 if ((RTL_R16 (CSCR) & in rtl8139_tune_twister()
2184 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit; in rtl8139_interrupt()
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| /openbmc/qemu/hw/net/ |
| H A D | rtl8139.c | 131 CSCR = 0x74, /* Chip Status and Configuration Register. */ enumerator
453 uint16_t CSCR; member
1207 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; in rtl8139_reset_phy()
2497 uint16_t ret = s->CSCR; in rtl8139_CSCR_read()
3041 case CSCR: in rtl8139_io_readw()
3196 VMSTATE_UINT16(CSCR, RTL8139State),
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| /openbmc/u-boot/drivers/net/ |
| H A D | rtl8139.c | 124 CSCR=0x74, /* chip status and configuration register */ enumerator
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| /openbmc/linux/drivers/net/usb/ |
| H A D | rtl8150.c | 40 #define CSCR 0x014C /* This one has the link status */ macro
720 get_registers(dev, CSCR, 2, &tmp); in set_carrier()
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| /openbmc/u-boot/arch/arm/lib/ |
| H A D | asm-offsets.c | 80 DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); in main()
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| /openbmc/u-boot/arch/arm/include/asm/arch-imx/ |
| H A D | imx-regs.h | 92 #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ macro
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