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Searched refs:CS1 (Results 1 – 25 of 93) sorted by relevance

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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-sx93246 SX9324 has 3 inputs, CS0, CS1 and CS2. Hardware layout
19 while CS1 and CS2 are used as shields.
21 [PH1], CS1 is measured, CS0 and CS2 are shield:
23 [PH2], CS2 is measured, CS0 and CS1 are shield:
25 [PH3], CS1 and CS2 are measured (combo mode):
H A Dsysfs-class-watchdog111 chip at CS1.
114 from (CS0->CS1, CS1->CS0) to (CS0->CS0,
115 CS1->CS1).
121 For alternate boot mode (booted from CS1 due to wdt2
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c172 write_sdrc_timings(CS1, sdrc_actim_base1, &timings); in do_sdrc_init()
183 if (cs == CS1) { in do_sdrc_init()
210 do_sdrc_init(CS1, NOT_EARLY); in dram_init()
211 size1 = get_sdr_cs_size(CS1); in dram_init()
223 size1 = get_sdr_cs_size(CS1); in dram_init_banksize()
227 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); in dram_init_banksize()
H A Demif4.c138 size1 = get_sdr_cs_size(CS1); in dram_init()
149 size1 = get_sdr_cs_size(CS1); in dram_init_banksize()
153 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); in dram_init_banksize()
/openbmc/linux/sound/soc/intel/catpt/
H A Ddsp.c222 catpt_updatel_shim(cdev, CS1, CATPT_CS_STALL, val); in catpt_dsp_stall()
224 return catpt_readl_poll_shim(cdev, CS1, in catpt_dsp_stall()
234 catpt_updatel_shim(cdev, CS1, CATPT_CS_RST, val); in catpt_dsp_reset()
236 return catpt_readl_poll_shim(cdev, CS1, in catpt_dsp_reset()
265 reg = catpt_readl_shim(cdev, CS1) & CATPT_CS_LPCS; in catpt_dsp_select_lpclock()
298 catpt_updatel_shim(cdev, CS1, mask, val); in catpt_dsp_select_lpclock()
329 catpt_writel_shim(cdev, CS1, CATPT_CS_DEFAULT); in catpt_dsp_set_regs_defaults()
366 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), in catpt_dsp_power_down()
428 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), in catpt_dsp_power_up()
/openbmc/linux/drivers/staging/fbtft/
H A Dfb_agm1264k-fl.c33 #define CS1 gpio.aux[1] macro
106 if (!par->CS1) { in verify_gpios()
136 par->CS1 = gpio->gpio; in request_gpios_match()
185 gpiod_set_value(par->CS1, 1); in write_reg8_bus8()
189 gpiod_set_value(par->CS1, 0); in write_reg8_bus8()
388 gpiod_set_value(par->CS1, 0); in write_vmem()
/openbmc/u-boot/doc/
H A DREADME.fsl-ddr31 |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
32 |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
37 | |CS0 Only| | | {CS0+CS1} | |
40 | |CS0 Only| | | {CS0+CS1} | |
43 | |CS0 Only| | | {CS0+CS1} | |
46 | | | | | {CS0+CS1} | |
49 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
408 DDR Chip-Select Interleaving Mode: CS0+CS1
/openbmc/u-boot/board/freescale/mpc8315erdb/
H A DREADME38 0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
42 is CS1.
/openbmc/u-boot/board/Marvell/openrd/
H A Dkwbimage.cfg128 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
134 # bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
136 # bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,ocelot_pcb.dtsi40 reg = <1>; /* CS1 */
/openbmc/u-boot/board/renesas/sh7785lcr/
H A DREADME.sh7785lcr26 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
27 0x06000000 - 0x07ffffff(CS1) | reserved | I2C
/openbmc/u-boot/board/freescale/mpc8313erdb/
H A DREADME38 0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K
45 is CS1.
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt39 - cs1-used : Have this property if CS1 of this EMIF
41 part attached to CS1, it should be the same type as the one on CS0,
/openbmc/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp46x-ixdp465.dts26 /* 32 MB of Flash mapped in at CS0 and CS1 */
H A Dintel-ixp42x-adi-coyote.dts43 * mapped in at CS0 and CS1
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3430-sdp.dts51 <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */
104 reg = <1 0 4>; /* CS1, offset 0, IO size 4 */
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg150 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
153 # bit3-2: 1, CS1 hit selected
164 # bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
/openbmc/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb125.dts61 reg = <1>; /* CS1 */
/openbmc/u-boot/board/amazon/kc1/
H A Dkc1.c56 if (cs == CS1) in emif_get_device_details()
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg138 # bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
140 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
/openbmc/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg134 # bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
136 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
/openbmc/u-boot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg135 # bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
137 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-370-xp.dtsi271 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
289 <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmotionpro.dts94 // 8-bit DualPort SRAM on LocalPlus Bus CS1
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl-colibri-eval-v3.dts131 /* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */

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