| /openbmc/linux/arch/arm64/kvm/ |
| H A D | sys_regs.h | 18 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
24 u8 CRm; member
34 .CRm = sys_reg_CRm(reg), \
41 .CRm = ((esr) >> 1) & 0xf, \
48 .CRm = ((esr) >> 1) & 0xf, \
66 u8 CRm; member
112 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); in print_sys_reg_msg()
203 if (i1->CRm != i2->CRm) in cmp_sys_reg()
204 return i1->CRm - i2->CRm; in cmp_sys_reg()
240 #define CRm(_x) .CRm = _x macro
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| H A D | sys_regs.c | 538 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; in trap_bvr()
545 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); in trap_bvr()
553 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; in set_bvr()
560 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; in get_bvr()
567 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; in reset_bvr()
575 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; in trap_bcr()
582 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); in trap_bcr()
590 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; in set_bcr()
597 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; in get_bcr()
604 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; in reset_bcr()
[all …]
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| H A D | trace_handle_exit.h | 171 __field(u8, CRm)
183 __entry->CRm = reg->CRm;
190 __entry->CRm, __entry->Op2,
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| /openbmc/linux/arch/arm/include/asm/vdso/ |
| H A D | cp15.h | 14 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ argument
15 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
16 #define __ACCESS_CP15_64(Op1, CRm) \ argument
17 "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
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| /openbmc/linux/arch/arm64/kvm/hyp/nvhe/ |
| H A D | sys_regs.c | 327 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
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| /openbmc/linux/tools/arch/arm64/include/asm/ |
| H A D | sysreg.h | 105 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ argument
106 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
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| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | sysreg.h | 112 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ argument
113 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
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| /openbmc/linux/Documentation/arch/arm64/ |
| H A D | cpu-feature-registers.rst | 95 Op0=3, Op1=0, CRn=0, CRm=0,2,3,4,5,6,7
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| /openbmc/linux/Documentation/virt/kvm/devices/ |
| H A D | arm-vgic-v3.rst | 190 | Op 0 | Op1 | CRn | CRm | Op2 |
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | a64.decode | 235 # The canonical NOP has CRm == op2 == 0, but all of the space
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| /openbmc/libcper/specification/document/ |
| H A D | cper-json-specification.tex | 1263 mrsEncoding.crm & uint64 & MRS Encoding CRm.\\
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