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Searched refs:CR1 (Results 1 – 17 of 17) sorted by relevance

/openbmc/u-boot/board/renesas/sh7752evb/
H A Dspi-boot.c27 #define CR1 0xFE002008 macro
70 spi_write(0x02, CR1); in spi_reset()
75 spi_write(0x00, CR1); in spi_reset()
97 spi_write(spi_read(CR1) | SPI_SSDB, CR1); in spi_read_flash()
98 spi_write(spi_read(CR1) | SPI_SSA, CR1); in spi_read_flash()
104 spi_write(0, CR1); in spi_read_flash()
/openbmc/qemu/hw/char/
H A Dstm32l4x5_usart.c35 REG32(CR1, 0x00)
36 FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */
37 FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */
38 FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */
39 FIELD(CR1, DEAT, 21, 5) /* Driver Enable assertion time */
40 FIELD(CR1, DEDT, 16, 5) /* Driver Enable de-assertion time */
41 FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */
42 FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */
43 FIELD(CR1, MME, 13, 1) /* Mute mode enable */
44 FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */
[all …]
/openbmc/u-boot/board/renesas/sh7753evb/
H A Dspi-boot.c23 #define CR1 0xFE002008 macro
75 spi_write(0x02, CR1); in spi_reset()
80 spi_write(0x00, CR1); in spi_reset()
110 spi_write(spi_read(CR1) | SPI_SSDB, CR1); in spi_read_flash()
111 spi_write(spi_read(CR1) | SPI_SSA, CR1); in spi_read_flash()
117 spi_write(0, CR1); in spi_read_flash()
/openbmc/u-boot/board/renesas/sh7757lcr/
H A Dspi-boot.c31 #define CR1 0xFE002008 macro
69 spi_write(0xfe, CR1); in spi_reset()
72 spi_write(0x00, CR1); in spi_reset()
92 spi_write(spi_read(CR1) | SPI_SSDB, CR1); in spi_read_flash()
93 spi_write(spi_read(CR1) | SPI_SSA, CR1); in spi_read_flash()
/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_usart-test.c22 REG32(CR1, 0x00)
23 FIELD(CR1, M1, 28, 1)
24 FIELD(CR1, OVER8, 15, 1)
25 FIELD(CR1, M0, 12, 1)
26 FIELD(CR1, PCE, 10, 1)
27 FIELD(CR1, TXEIE, 7, 1)
28 FIELD(CR1, RXNEIE, 5, 1)
29 FIELD(CR1, TE, 3, 1)
30 FIELD(CR1, RE, 2, 1)
31 FIELD(CR1, UE, 0, 1)
/openbmc/linux/arch/powerpc/include/uapi/asm/
H A Dtermbits.h89 #define CR1 0x01000 macro
/openbmc/linux/include/uapi/asm-generic/
H A Dtermbits.h75 #define CR1 0x00200 macro
/openbmc/linux/arch/parisc/include/uapi/asm/
H A Dtermbits.h75 #define CR1 0x00200 macro
/openbmc/linux/arch/alpha/include/uapi/asm/
H A Dtermbits.h94 #define CR1 0x01000 macro
/openbmc/linux/arch/mips/include/uapi/asm/
H A Dtermbits.h95 #define CR1 0x00200 macro
/openbmc/linux/arch/sparc/include/uapi/asm/
H A Dtermbits.h92 #define CR1 0x00200 macro
/openbmc/qemu/hw/arm/
H A Dsmmuv3-internal.h126 REG32(CR1, 0x28)
/openbmc/qemu/hw/net/can/
H A Dxlnx-versal-canfd.c268 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR1, 1, 1)
/openbmc/linux/drivers/dma/
H A Dpl330.c133 #define CR1 0xe04 macro
/openbmc/qemu/linux-user/
H A Dstrace.c1407 ENUM_TARGET(CR1),
H A Dsyscall.c5718 { TARGET_CRDLY, TARGET_CR1, CRDLY, CR1 },
/openbmc/libcper/specification/document/
H A Dcper-json-specification.tex605 cr1 & uint64 & The CR1 register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.…
677 cr1 & uint64 & The CR1 register.\\