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Searched refs:CPUTLBEntry (Results 1 – 13 of 13) sorted by relevance

/openbmc/qemu/include/exec/
H A Dtlb-common.h25 typedef union CPUTLBEntry { union
41 } CPUTLBEntry; typedef
43 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
53 CPUTLBEntry *table;
/openbmc/qemu/accel/tcg/
H A Dcputlb.c102 static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry, in tlb_read_idx()
106 QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) != in tlb_read_idx()
108 QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) != in tlb_read_idx()
110 QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) != in tlb_read_idx()
129 static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry) in tlb_addr_write()
144 static inline CPUTLBEntry *tlb_entry(CPUState *cpu, uintptr_t mmu_idx, in tlb_entry()
262 fast->table = g_try_new(CPUTLBEntry, new_size); in tlb_mmu_resize_locked()
282 fast->table = g_try_new(CPUTLBEntry, new_size); in tlb_mmu_resize_locked()
314 fast->table = g_new(CPUTLBEntry, n_entries); in tlb_mmu_init()
446 static bool tlb_hit_page_mask_anyprot(CPUTLBEntry *tlb_entry, in tlb_hit_page_mask_anyprot()
[all …]
/openbmc/qemu/include/hw/core/
H A Dcpu.h288 CPUTLBEntry vtable[CPU_VTLB_SIZE];
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.c.inc1083 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
1084 : offsetof(CPUTLBEntry, addr_write);
1085 int add_off = offsetof(CPUTLBEntry, addend);
1098 /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */
/openbmc/qemu/tcg/mips/
H A Dtcg-target.c.inc1230 int add_off = offsetof(CPUTLBEntry, addend);
1231 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
1232 : offsetof(CPUTLBEntry, addr_write);
1254 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */
/openbmc/qemu/tcg/arm/
H A Dtcg-target.c.inc1438 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
1439 : offsetof(CPUTLBEntry, addr_write);
1460 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
1484 offsetof(CPUTLBEntry, addend));
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc1018 is_ld ? offsetof(CPUTLBEntry, addr_read)
1019 : offsetof(CPUTLBEntry, addr_write));
1021 offsetof(CPUTLBEntry, addend));
/openbmc/qemu/docs/devel/
H A Dmulti-thread-tcg.rst202 - TLB Update (update a CPUTLBEntry, via tlb_set_page_with_attrs)
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.c.inc1783 /* Add the tlb_table pointer, forming the CPUTLBEntry address. */
1789 is_ld ? offsetof(CPUTLBEntry, addr_read)
1790 : offsetof(CPUTLBEntry, addr_write));
1792 offsetof(CPUTLBEntry, addend));
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc1758 is_ld ? offsetof(CPUTLBEntry, addr_read)
1759 : offsetof(CPUTLBEntry, addr_write));
1761 offsetof(CPUTLBEntry, addend));
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.c.inc2470 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
2471 : offsetof(CPUTLBEntry, addr_write);
2526 offsetof(CPUTLBEntry, addend));
2582 offsetof(CPUTLBEntry, addend));
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.c.inc1909 ofs = offsetof(CPUTLBEntry, addr_read);
1911 ofs = offsetof(CPUTLBEntry, addr_write);
1925 offsetof(CPUTLBEntry, addend));
/openbmc/qemu/tcg/i386/
H A Dtcg-target.c.inc2160 int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read)
2161 : offsetof(CPUTLBEntry, addr_write);
2234 offsetof(CPUTLBEntry, addend));