Searched refs:CPSR_M (Results 1 – 9 of 9) sorted by relevance
593 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER()602 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { in HELPER()610 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER()625 int curmode = env->uncached_cpsr & CPSR_M; in msr_mrs_banked_exc_checks()689 if (tgtmode == (env->uncached_cpsr & CPSR_M)) { in HELPER()728 if (tgtmode == (env->uncached_cpsr & CPSR_M)) { in HELPER()
720 switch (spsr & CPSR_M) { in el_from_spsr()
7067 mask |= CPSR_M; in trans_CPS()
156 if ((cpsr & CPSR_M) != ARM_CPU_MODE_USR || in set_mcontext()
10473 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || in bad_mode_switch()10496 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && in bad_mode_switch()10526 (mask & (CPSR_M | CPSR_E | CPSR_IL)); in cpsr_write()10612 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { in cpsr_write()10613 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { in cpsr_write()10621 mask &= ~CPSR_M; in cpsr_write()10622 } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { in cpsr_write()10632 mask &= ~CPSR_M; in cpsr_write()10649 switch_mode(env, val & CPSR_M); in cpsr_write()10688 old_mode = env->uncached_cpsr & CPSR_M; in switch_mode()[all …]
2128 i = bank_number(env->uncached_cpsr & CPSR_M); in kvm_arch_put_registers()2321 i = bank_number(env->uncached_cpsr & CPSR_M); in kvm_arch_get_registers()
1395 #define CPSR_M (0x1fU) macro2509 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { in arm_is_el3_or_mon()
673 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); in arm_emulate_firmware_reset()1443 (psr & CPSR_M) != ARM_CPU_MODE_MON) { in arm_cpu_dump_state()
1242 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; in aarch32_cpsr_valid_mask()