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Searched refs:CP0TCSt_IXMT (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/mips/
H A Dinternal.h178 !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); in cpu_mips_hw_interrupts_enabled()
H A Dcpu.h488 #define CP0TCSt_IXMT 10 macro
H A Dcpu-defs.c.inc293 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |