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Searched refs:CP0C5_SBRI (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc489 (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
529 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
761 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
801 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
914 (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
H A Dinternal.h351 (env->CP0_Config5 & (1 << CP0C5_SBRI))) { in compute_hflags()
H A Dcpu.h948 #define CP0C5_SBRI 6 macro