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Searched refs:CP0C5_MI (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/mips/tcg/sysemu/
H A Dtlb_helper.c85 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbinv()
115 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbwi()
171 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbp()
234 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbr()
396 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_map_address()
1366 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_invalidate_tlb()
H A Dcp0_helper.c1279 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in helper_mtc0_config5()
1337 if ((env->CP0_Config5 >> CP0C5_MI) & 1) { in helper_mtc0_watchhi()
/openbmc/qemu/target/mips/
H A Dcpu.h939 #define CP0C5_MI 17 macro
H A Dcpu.c302 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in mips_cpu_reset_hold()
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c15095 ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1; in mips_tr_init_disas_context()