Searched refs:CONFIG_SYS_DDR_ZQ_CONTROL (Results 1 – 16 of 16) sorted by relevance
| /openbmc/u-boot/board/freescale/bsc9132qds/ |
| H A D | spl_minimal.c | 40 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); in sdram_init()
60 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); in sdram_init()
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| H A D | ddr.c | 37 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
64 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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| /openbmc/u-boot/board/freescale/p1010rdb/ |
| H A D | ddr.c | 40 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
67 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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| /openbmc/u-boot/board/freescale/p1_twr/ |
| H A D | ddr.c | 46 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, in fixed_sdram()
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| /openbmc/u-boot/board/freescale/bsc9131rdb/ |
| H A D | spl_minimal.c | 47 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); in sdram_init()
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| H A D | ddr.c | 38 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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| /openbmc/u-boot/board/Arcturus/ucp1020/ |
| H A D | ddr.c | 106 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, in fixed_sdram()
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| /openbmc/u-boot/include/configs/ |
| H A D | BSC9131RDB.h | 92 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 macro
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| H A D | p1_twr.h | 90 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 macro
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| H A D | UCP1020.h | 158 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 macro
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| H A D | BSC9132QDS.h | 129 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 macro
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| H A D | P1022DS.h | 164 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 macro
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| H A D | P1010RDB.h | 233 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 macro
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| H A D | p1_p2_rdb_pc.h | 297 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 macro
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| /openbmc/u-boot/board/freescale/p1_p2_rdb_pc/ |
| H A D | ddr.c | 238 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, in fixed_sdram()
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| /openbmc/u-boot/scripts/ |
| H A D | config_whitelist.txt | 2428 CONFIG_SYS_DDR_ZQ_CONTROL
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