Searched refs:CONFIG_SYS_DDR_TIMING_5 (Results 1 – 18 of 18) sorted by relevance
| /openbmc/u-boot/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 67 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 macro
102 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
134 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
166 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
198 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
230 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
262 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
294 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
326 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /openbmc/u-boot/include/configs/ |
| H A D | BSC9132QDS.h | 171 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 macro
177 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 macro
183 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 macro
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| H A D | BSC9131RDB.h | 99 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 macro
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| H A D | p1_twr.h | 98 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
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| H A D | UCP1020.h | 170 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
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| H A D | MPC8569MDS.h | 103 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
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| H A D | P1022DS.h | 163 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 macro
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| H A D | P1010RDB.h | 240 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
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| H A D | p1_p2_rdb_pc.h | 305 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
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| /openbmc/u-boot/board/freescale/bsc9132qds/ |
| H A D | ddr.c | 36 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
63 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /openbmc/u-boot/board/freescale/p1010rdb/ |
| H A D | ddr.c | 39 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
66 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /openbmc/u-boot/board/freescale/p1_twr/ |
| H A D | ddr.c | 45 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, in fixed_sdram()
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| /openbmc/u-boot/board/freescale/bsc9131rdb/ |
| H A D | spl_minimal.c | 46 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); in sdram_init()
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| H A D | ddr.c | 37 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /openbmc/u-boot/board/Arcturus/ucp1020/ |
| H A D | ddr.c | 105 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, in fixed_sdram()
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| /openbmc/u-boot/board/freescale/p1_p2_rdb_pc/ |
| H A D | ddr.c | 237 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, in fixed_sdram()
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| /openbmc/u-boot/board/freescale/mpc8569mds/ |
| H A D | mpc8569mds.c | 252 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); in fixed_sdram()
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| /openbmc/u-boot/scripts/ |
| H A D | config_whitelist.txt | 2418 CONFIG_SYS_DDR_TIMING_5
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