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Searched refs:CONFIG_SYS_CACHELINE_SIZE (Results 1 – 25 of 78) sorted by relevance

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/openbmc/u-boot/arch/x86/include/asm/
H A Dcache.h13 #ifndef CONFIG_SYS_CACHELINE_SIZE
14 #define CONFIG_SYS_CACHELINE_SIZE 64 macro
17 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
/openbmc/u-boot/arch/arm/cpu/pxa/
H A Dcache.c25 start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); in invalidate_dcache_range()
26 stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); in invalidate_dcache_range()
30 start += CONFIG_SYS_CACHELINE_SIZE; in invalidate_dcache_range()
/openbmc/u-boot/arch/powerpc/lib/
H A Dcache.c16 start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); in flush_cache()
20 addr += CONFIG_SYS_CACHELINE_SIZE) { in flush_cache()
28 addr += CONFIG_SYS_CACHELINE_SIZE) { in flush_cache()
/openbmc/u-boot/drivers/bootcount/
H A Dbootcount.c15 CONFIG_SYS_CACHELINE_SIZE); in bootcount_store()
22 CONFIG_SYS_CACHELINE_SIZE); in bootcount_store()
28 CONFIG_SYS_CACHELINE_SIZE); in bootcount_store()
/openbmc/u-boot/arch/microblaze/include/asm/
H A Dcache.h15 #ifdef CONFIG_SYS_CACHELINE_SIZE
16 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
/openbmc/u-boot/arch/riscv/include/asm/
H A Dcache.h18 #ifdef CONFIG_SYS_CACHELINE_SIZE
19 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
/openbmc/u-boot/arch/arm/cpu/arm926ejs/
H A Dcache.c33 start += CONFIG_SYS_CACHELINE_SIZE; in invalidate_dcache_range()
44 start += CONFIG_SYS_CACHELINE_SIZE; in flush_dcache_range()
/openbmc/u-boot/arch/arm/cpu/arm11/
H A Dcpu.c73 start += CONFIG_SYS_CACHELINE_SIZE; in invalidate_dcache_range()
84 start += CONFIG_SYS_CACHELINE_SIZE; in flush_dcache_range()
/openbmc/u-boot/arch/nds32/include/asm/
H A Dcache.h57 #ifdef CONFIG_SYS_CACHELINE_SIZE
58 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dsec_entry_cpu1.S84 mov r1, #CONFIG_SYS_CACHELINE_SIZE
113 .balign CONFIG_SYS_CACHELINE_SIZE
114 .rept CONFIG_SYS_CACHELINE_SIZE/4
/openbmc/u-boot/arch/arm/lib/
H A Dcache.c52 if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) in check_cache_range()
55 if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) in check_cache_range()
H A Dcache-cp15.c82 startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); in mmu_set_region_dcache_behaviour()
84 stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE); in mmu_set_region_dcache_behaviour()
/openbmc/u-boot/arch/mips/mach-jz47xx/
H A Dstart.S71 addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
78 addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dcache.h31 #ifndef CONFIG_SYS_CACHELINE_SIZE
32 #define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES macro
/openbmc/u-boot/arch/m68k/include/asm/
H A Dcache.h197 #ifdef CONFIG_SYS_CACHELINE_SIZE
198 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
/openbmc/u-boot/drivers/net/
H A Dfsl_mcdmafec.c509 (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, in mcdmafec_initialize()
538 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, in mcdmafec_initialize()
541 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, in mcdmafec_initialize()
544 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); in mcdmafec_initialize()
552 fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); in mcdmafec_initialize()
H A Dmcffec.c548 (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, in mcffec_initialize()
577 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, in mcffec_initialize()
580 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, in mcffec_initialize()
583 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); in mcffec_initialize()
591 fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); in mcffec_initialize()
H A Dftgmac100.h187 } __aligned(CONFIG_SYS_CACHELINE_SIZE);
222 } __aligned(CONFIG_SYS_CACHELINE_SIZE);
/openbmc/u-boot/arch/sandbox/include/asm/
H A Dcache.h22 #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN macro
/openbmc/u-boot/arch/mips/include/asm/
H A Dcache.h19 #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN macro
/openbmc/u-boot/arch/arc/include/asm/
H A Dcache.h20 #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN macro
/openbmc/u-boot/include/configs/
H A Drk3368_common.h11 #define CONFIG_SYS_CACHELINE_SIZE 64 macro
H A Drk3188_common.h9 #define CONFIG_SYS_CACHELINE_SIZE 64 macro
/openbmc/u-boot/arch/arm/include/asm/
H A Dcache.h50 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
/openbmc/u-boot/drivers/usb/dwc3/
H A Dio.h22 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE

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