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Searched refs:CLK_TOP_VENCPLL (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c85 FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
209 CLK_TOP_VENCPLL,
232 CLK_TOP_VENCPLL,
397 CLK_TOP_VENCPLL,
413 CLK_TOP_VENCPLL,
/openbmc/linux/include/dt-bindings/clock/
H A Dmediatek,mt6795-clk.h87 #define CLK_TOP_VENCPLL 76 macro
H A Dmt8173-clk.h89 #define CLK_TOP_VENCPLL 79 macro
H A Dmt2712-clk.h99 #define CLK_TOP_VENCPLL 68 macro
H A Dmt2701-clk.h83 #define CLK_TOP_VENCPLL 73 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7623-clk.h14 #define CLK_TOP_VENCPLL 2 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c445 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),
H A Dclk-mt8173-topckgen.c524 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),
H A Dclk-mt2712.c106 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),
H A Dclk-mt2701.c32 FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m",