| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt8167-clk.h | 34 #define CLK_TOP_TVDPLL_D2 (CLK_TOP_NR_CLK + 10) macro
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| H A D | mt6797-clk.h | 97 #define CLK_TOP_TVDPLL_D2 87 macro
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| H A D | mediatek,mt6795-clk.h | 66 #define CLK_TOP_TVDPLL_D2 55 macro
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| H A D | mt8173-clk.h | 68 #define CLK_TOP_TVDPLL_D2 58 macro
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| H A D | mt8186-clk.h | 125 #define CLK_TOP_TVDPLL_D2 106 macro
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| H A D | mt6779-clk.h | 92 #define CLK_TOP_TVDPLL_D2 82 macro
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| H A D | mt2712-clk.h | 104 #define CLK_TOP_TVDPLL_D2 73 macro
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| H A D | mt8183-clk.h | 117 #define CLK_TOP_TVDPLL_D2 81 macro
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| H A D | mt2701-clk.h | 58 #define CLK_TOP_TVDPLL_D2 48 macro
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| H A D | mt8192-clk.h | 132 #define CLK_TOP_TVDPLL_D2 120 macro
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 152 FACTOR0(CLK_TOP_TVDPLL_D2, CLK_APMIXED_TVDPLL, 1, 2),
323 CLK_TOP_TVDPLL_D2,
330 CLK_TOP_TVDPLL_D2,
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 74 #define CLK_TOP_TVDPLL_D2 61 macro
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 421 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
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| H A D | clk-mt8173-topckgen.c | 500 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
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| H A D | clk-mt8186-topckgen.c | 60 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
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| H A D | clk-mt8167.c | 79 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
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| H A D | clk-mt6797.c | 77 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
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| H A D | clk-mt8183.c | 80 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
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| H A D | clk-mt2712.c | 111 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
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| H A D | clk-mt8192.c | 78 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
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| H A D | clk-mt6779.c | 78 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
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| H A D | clk-mt2701.c | 109 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
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| /openbmc/linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8186.dtsi | 1821 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
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