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Searched refs:CLK_TOP_SYSPLL_D7 (Results 1 – 22 of 22) sorted by relevance

/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c111 FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
209 CLK_TOP_SYSPLL_D7
262 CLK_TOP_SYSPLL_D7,
273 CLK_TOP_SYSPLL_D7,
H A Dclk-mt7623.c105 FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
115 FACTOR1(CLK_TOP_SYSPLL4_D2, CLK_TOP_SYSPLL_D7, 1, 2),
116 FACTOR1(CLK_TOP_SYSPLL4_D4, CLK_TOP_SYSPLL_D7, 1, 4),
362 CLK_TOP_SYSPLL_D7,
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7629-clk.h48 #define CLK_TOP_SYSPLL_D7 35 macro
H A Dmt7623-clk.h32 #define CLK_TOP_SYSPLL_D7 19 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dmt7629-clk.h45 #define CLK_TOP_SYSPLL_D7 35 macro
H A Dmt6797-clk.h59 #define CLK_TOP_SYSPLL_D7 49 macro
H A Dmediatek,mt6795-clk.h62 #define CLK_TOP_SYSPLL_D7 51 macro
H A Dmt8173-clk.h64 #define CLK_TOP_SYSPLL_D7 54 macro
H A Dmt6765-clk.h48 #define CLK_TOP_SYSPLL_D7 13 macro
H A Dmediatek,mt8365-clk.h28 #define CLK_TOP_SYSPLL_D7 18 macro
H A Dmt2712-clk.h47 #define CLK_TOP_SYSPLL_D7 16 macro
H A Dmt8183-clk.h82 #define CLK_TOP_SYSPLL_D7 46 macro
H A Dmt2701-clk.h15 #define CLK_TOP_SYSPLL_D7 5 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c416 FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1, 0),
H A Dclk-mt8173-topckgen.c495 FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1, 0),
H A Dclk-mt7629.c388 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
H A Dclk-mt6797.c39 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
H A Dclk-mt8183.c48 FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7, 0),
H A Dclk-mt2712.c55 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1, 7),
H A Dclk-mt8365.c47 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
H A Dclk-mt6765.c96 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
H A Dclk-mt2701.c61 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),