| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 106 #define CLK_TOP_SCP_SEL 92 macro
|
| H A D | mt7623-clk.h | 118 #define CLK_TOP_SCP_SEL 104 macro
|
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 102 #define CLK_TOP_SCP_SEL 92 macro
|
| H A D | mt7622-clk.h | 87 #define CLK_TOP_SCP_SEL 75 macro
|
| H A D | mediatek,mt6795-clk.h | 111 #define CLK_TOP_SCP_SEL 100 macro
|
| H A D | mt8173-clk.h | 113 #define CLK_TOP_SCP_SEL 103 macro
|
| H A D | mt6765-clk.h | 134 #define CLK_TOP_SCP_SEL 99 macro
|
| H A D | mediatek,mt8365-clk.h | 74 #define CLK_TOP_SCP_SEL 64 macro
|
| H A D | mt2701-clk.h | 105 #define CLK_TOP_SCP_SEL 94 macro
|
| H A D | mt8192-clk.h | 14 #define CLK_TOP_SCP_SEL 2 macro
|
| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 483 TOP_MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x90, 8, 3, 15, 0),
|
| H A D | clk-mt8173-topckgen.c | 568 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
|
| H A D | clk-mt7622.c | 432 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
|
| H A D | clk-mt7629.c | 504 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
|
| H A D | clk-mt8365.c | 417 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040,
|
| H A D | clk-mt8192.c | 554 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel",
|
| H A D | clk-mt6765.c | 379 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
|
| H A D | clk-mt2701.c | 525 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
|
| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7629.c | 391 MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31),
|
| H A D | clk-mt7623.c | 531 MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15),
|
| /openbmc/linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8173.dtsi | 562 clocks = <&topckgen CLK_TOP_SCP_SEL>;
|