Searched refs:CLK_TOP_AXISEL_D4 (Results 1 – 4 of 4) sorted by relevance
/openbmc/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt7623.c | 182 FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4), 649 GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2), 650 GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3), 651 GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4), 652 GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5), 653 GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6), 654 GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7), 655 GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8),
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/openbmc/u-boot/include/dt-bindings/clock/ |
H A D | mt7623-clk.h | 98 #define CLK_TOP_AXISEL_D4 85 macro
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | mt2701-clk.h | 170 #define CLK_TOP_AXISEL_D4 158 macro
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/openbmc/linux/drivers/clk/mediatek/ |
H A D | clk-mt2701.c | 140 FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4),
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