Home
last modified time | relevance | path

Searched refs:CLK_TOP_AUDINTBUS_SEL (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7623-clk.h116 #define CLK_TOP_AUDINTBUS_SEL 102 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dmt2701-clk.h99 #define CLK_TOP_AUDINTBUS_SEL 88 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt2701.c520 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c528 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31),