| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt8186-apmixedsys.c | 63 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0254, 0x0260, 0,
126 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x008C),
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| H A D | clk-mt8173-apmixedsys.c | 69 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0,
126 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c),
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| H A D | clk-mt8195-apmixedsys.c | 74 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0, 0xff000000,
157 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
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| H A D | clk-mt8192-apmixedsys.c | 81 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000,
139 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
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| H A D | clk-mt6795-apmixedsys.c | 53 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0),
107 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c),
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| H A D | clk-mt7981-apmixed.c | 49 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
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| H A D | clk-mt8135-apmixedsys.c | 42 …PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, …
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| H A D | clk-mt7986-apmixed.c | 47 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x0, 0, 32,
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| H A D | clk-mt8516-apmixedsys.c | 66 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
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| H A D | clk-mt8167-apmixedsys.c | 65 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
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| H A D | clk-mt8188-apmixedsys.c | 69 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0544, 0x0550, 0xff000000,
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| H A D | clk-mt2712-apmixedsys.c | 102 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,
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| H A D | clk-mt8365-apmixedsys.c | 93 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22,
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| H A D | clk-mt8183-apmixedsys.c | 133 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0,
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt7986-clk.h | 14 #define CLK_APMIXED_MMPLL 2 macro
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| H A D | mt8135-clk.h | 112 #define CLK_APMIXED_MMPLL 5 macro
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| H A D | mediatek,mt7981-clk.h | 190 #define CLK_APMIXED_MMPLL 2 macro
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| H A D | mt8516-clk.h | 16 #define CLK_APMIXED_MMPLL 3 macro
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| H A D | mediatek,mt6795-clk.h | 144 #define CLK_APMIXED_MMPLL 3 macro
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| H A D | mt8173-clk.h | 160 #define CLK_APMIXED_MMPLL 5 macro
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| H A D | mt6765-clk.h | 15 #define CLK_APMIXED_MMPLL 5 macro
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| H A D | mediatek,mt8365-clk.h | 236 #define CLK_APMIXED_MMPLL 5 macro
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| H A D | mt8186-clk.h | 270 #define CLK_APMIXED_MMPLL 6 macro
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 50 PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
144 FACTOR0(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1),
145 FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 180 #define CLK_APMIXED_MMPLL 3 macro
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