Home
last modified time | relevance | path

Searched refs:CLK_APMIXED_MAINPLL (Results 1 – 25 of 47) sorted by relevance

12

/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c50 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
100 FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
101 FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
102 FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
103 FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
104 FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
105 FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
106 FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
107 FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
108 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
[all …]
H A Dclk-mt7623.c46 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR,
101 FACTOR0(CLK_TOP_SYSPLL, CLK_APMIXED_MAINPLL, 1, 1),
102 FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
103 FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
104 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
105 FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek.txt71 <&apmixedsys CLK_APMIXED_MAINPLL>;
193 <&apmixedsys CLK_APMIXED_MAINPLL>;
205 <&apmixedsys CLK_APMIXED_MAINPLL>;
217 <&apmixedsys CLK_APMIXED_MAINPLL>;
229 <&apmixedsys CLK_APMIXED_MAINPLL>;
/openbmc/u-boot/arch/arm/dts/
H A Dmt7623.dtsi32 <&apmixedsys CLK_APMIXED_MAINPLL>;
42 <&apmixedsys CLK_APMIXED_MAINPLL>;
52 <&apmixedsys CLK_APMIXED_MAINPLL>;
62 <&apmixedsys CLK_APMIXED_MAINPLL>;
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8186-apmixedsys.c57 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0244, 0x0250, 0xff000000,
125 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x0078),
H A Dclk-mt8173-apmixedsys.c65 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21,
123 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60),
H A Dclk-mt8195-apmixedsys.c76 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0, 0xff000000,
158 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
H A Dclk-mt8192-apmixedsys.c73 PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000,
140 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
H A Dclk-mt6795-apmixedsys.c49 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
104 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60),
H A Dclk-mt8135-apmixedsys.c40 …PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x2…
H A Dclk-mt8516-apmixedsys.c62 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
H A Dclk-mt8167-apmixedsys.c61 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
H A Dclk-mt8188-apmixedsys.c71 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x045C, 0x0468, 0xff000000,
H A Dclk-mt7622-apmixedsys.c61 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
H A Dclk-mt2712-apmixedsys.c80 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
H A Dclk-mt8365-apmixedsys.c85 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001,
/openbmc/u-boot/arch/arm/mach-mediatek/mt7629/
H A Dinit.c30 [CLK_APMIXED_MAINPLL] = 1120000000, in mtk_pll_early_init()
/openbmc/linux/include/dt-bindings/clock/
H A Dmt8135-clk.h110 #define CLK_APMIXED_MAINPLL 3 macro
H A Dmt7629-clk.h156 #define CLK_APMIXED_MAINPLL 1 macro
H A Dmt8516-clk.h14 #define CLK_APMIXED_MAINPLL 1 macro
H A Dmt7622-clk.h171 #define CLK_APMIXED_MAINPLL 1 macro
H A Dmt6797-clk.h108 #define CLK_APMIXED_MAINPLL 1 macro
H A Dmediatek,mt6795-clk.h142 #define CLK_APMIXED_MAINPLL 1 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7629-clk.h160 #define CLK_APMIXED_MAINPLL 1 macro
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365.dtsi140 <&apmixedsys CLK_APMIXED_MAINPLL>;
160 <&apmixedsys CLK_APMIXED_MAINPLL>;
180 <&apmixedsys CLK_APMIXED_MAINPLL>;
200 <&apmixedsys CLK_APMIXED_MAINPLL>;

12