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Searched refs:CLKID_USB0_DDR_BRIDGE (Results 1 – 13 of 13) sorted by relevance

/openbmc/u-boot/include/dt-bindings/clock/
H A Daxg-clkc.h58 #define CLKID_USB0_DDR_BRIDGE 49 macro
H A Dgxbb-clkc.h71 #define CLKID_USB0_DDR_BRIDGE 65 macro
/openbmc/linux/include/dt-bindings/clock/
H A Daxg-clkc.h60 #define CLKID_USB0_DDR_BRIDGE 49 macro
H A Dgxbb-clkc.h73 #define CLKID_USB0_DDR_BRIDGE 65 macro
H A Dmeson8b-clkc.h72 #define CLKID_USB0_DDR_BRIDGE 65 macro
/openbmc/u-boot/arch/arm/dts/
H A Dmeson-gxbb.dtsi41 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
/openbmc/u-boot/drivers/clk/
H A Dclk_meson.c140 MESON_GATE(CLKID_USB0_DDR_BRIDGE, HHI_GCLK_MPEG2, 9),
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb.dtsi42 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
/openbmc/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8.dtsi784 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
H A Dmeson8b.dtsi755 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
/openbmc/linux/drivers/clk/meson/
H A Dmeson8b.c2841 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
3045 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
3260 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
H A Dgxbb.c2798 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
3006 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
H A Daxg.c1945 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,