Searched refs:CHSCCDR_CLK_SEL_LDB_DI0 (Results 1 – 15 of 15) sorted by relevance
167 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
454 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in enable_lvds()542 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in enable_spi_display()
467 (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display_b850v3()513 (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display_bx50v3()
407 (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display_clock()
515 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()517 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
499 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()501 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
650 setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()652 CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
415 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
481 (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
407 (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
596 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
780 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
510 #define CHSCCDR_CLK_SEL_LDB_DI0 3 macro
718 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
479 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()