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Searched refs:CCCR (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/clk/pxa/
H A Dclk-pxa25x.c103 unsigned long cccr = readl(clk_regs + CCCR); in clk_pxa25x_memory_get_rate()
207 unsigned long cccr = readl(clk_regs + CCCR); in clk_pxa25x_run_get_rate()
218 unsigned long clkcfg, cccr = readl(clk_regs + CCCR); in clk_pxa25x_cpll_get_rate()
250 pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, clk_regs + CCCR); in clk_pxa25x_cpll_set_rate()
H A Dclk-pxa27x.c241 pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, clk_regs + CCCR); in clk_pxa27x_cpll_set_rate()
253 unsigned long cccr = readl(clk_regs + CCCR); in clk_pxa27x_lcd_base_get_rate()
396 unsigned long cccr = readl(clk_regs + CCCR); in clk_pxa27x_memory_get_rate()
415 unsigned long cccr = readl(clk_regs + CCCR); in clk_pxa27x_memory_get_parent()
H A Dclk-pxa2xx.h5 #define CCCR (0x0000) /* Core Clock Configuration Register */ macro
/openbmc/linux/arch/arm/mach-pxa/
H A Dsleep.S70 ldr r6, =CCCR
73 ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value
113 ldr r6, =CCCR
H A Dpxa2xx-regs.h134 #define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */ macro
/openbmc/u-boot/arch/arm/cpu/pxa/
H A Dpxa2xx.c229 writel(CONFIG_SYS_CCCR, CCCR); in pxa_clock_setup()
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h1040 #define CCCR 0x41300000 /* Core Clock Configuration Register */ macro