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Searched refs:CACHELINE_SIZE (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/drivers/usb/dwc3/
H A Dio.h22 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
52 flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE)); in dwc3_flush_cache()
/openbmc/linux/tools/testing/selftests/powerpc/security/
H A Dflush_utils.c34 for (unsigned long j = 0; j < zero_size; j += CACHELINE_SIZE) in syscall_loop()
46 for (unsigned long j = 0; j < zero_size; j += CACHELINE_SIZE) in syscall_loop_uaccess()
H A Dentry_flush.c59 p = (char *)memalign(zero_size, CACHELINE_SIZE); in entry_flush_test()
72 l1d_misses_expected = iterations * (zero_size / CACHELINE_SIZE - 2); in entry_flush_test()
H A Drfi_flush.c60 p = (char *)memalign(zero_size, CACHELINE_SIZE); in rfi_flush_test()
73 l1d_misses_expected = iterations * (zero_size / CACHELINE_SIZE - 2); in rfi_flush_test()
H A Duaccess_flush.c73 p = (char *)memalign(zero_size, CACHELINE_SIZE); in uaccess_flush_test()
86 l1d_misses_expected = iterations * (zero_size / CACHELINE_SIZE - 2); in uaccess_flush_test()
H A Dflush_utils.h10 #define CACHELINE_SIZE 128 macro
/openbmc/linux/lib/zstd/common/
H A Dcompiler.h96 #define CACHELINE_SIZE 64 macro
102 for (_pos=0; _pos<_size; _pos+=CACHELINE_SIZE) { \
/openbmc/u-boot/drivers/usb/host/
H A Dxhci-mem.c26 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
38 flush_dcache_range(addr & ~(CACHELINE_SIZE - 1), in xhci_flush_cache()
39 ALIGN(addr + len, CACHELINE_SIZE)); in xhci_flush_cache()
53 invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1), in xhci_inval_cache()
54 ALIGN(addr + len, CACHELINE_SIZE)); in xhci_inval_cache()
192 size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE); in xhci_malloc()
/openbmc/linux/lib/zstd/decompress/
H A Dzstd_decompress_block.c1657 …PREFETCH_L1(match); PREFETCH_L1(match+CACHELINE_SIZE); /* note : it's safe to invoke PREFETCH() …