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Searched refs:BOOL_TO_MASK (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dtime_helper.c30 riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1)); in riscv_vstimer_cb()
36 riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1)); in riscv_stimer_cb()
59 riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1)); in riscv_timer_write_timecmp()
61 riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1)); in riscv_timer_write_timecmp()
69 riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0)); in riscv_timer_write_timecmp()
71 riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0)); in riscv_timer_write_timecmp()
H A Dpmu.c133 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); in riscv_pmu_incr_ctr_rv32()
172 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); in riscv_pmu_incr_ctr_rv64()
517 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); in pmu_timer_trigger_irq()
H A Dcpu.h588 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ macro
H A Dcpu.c1272 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); in riscv_cpu_set_irq()
1281 BOOL_TO_MASK(level | env->software_seip)); in riscv_cpu_set_irq()
1307 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); in riscv_cpu_set_irq()
H A Dcsr.c3869 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); in write_hgeie()